Intel 440GX manual Uni-Processor UP Slot 1 Checklist, Dual-Processor DP Slot 1 Checklist

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Design Checklist

3.3.4Uni-Processor (UP) Slot 1 Checklist

•A UP system must connect BREQ0# of the Slot 1 connector to the 82443GX’s BREQ0# signal. This will assign an agent ID of 0 to the processor. BREQ1# on the Slot 1 connector is left as a no connect.

•For a UP design, one set of GTL+ termination resistors (56 ohm) are recommended on the

motherboard (dual ended termination). The second set of terminations are provided on the Intel® Pentium® II processor. Single ended termination (processor termination only) may be achieved provided the trace lengths adhere to the very restrictive lengths given in the layout guidelines.

•FRCERR# may be left as a no connect for a UP design. On board termination resistors are not required since they are provided on the Intel® Pentium® II processor.

3.3.5Dual-Processor (DP) Slot 1 Checklist

•A DP system must cross connect BREQ[1:0]# of the Slot 1 connector to the 82443GX’s BREQ0# signal, i.e. BREQ0# should be tied to BREQ1# on the other processor.

•No onboard termination is required because termination is provided on the Intel® Pentium® II processor.

•FRCERR# may be left as a no connect for a DP design if FRC mode is not supported. On board termination resistors are not required since they are provided on the Intel® Pentium® II processors.

•Each processor site should have an isolated VccCORE power plane. Contact your VRM vendor for availability of VRMs with current sharing capabilities if desired.

•The SLOTOCC# signal can be used to block the system from booting if two sets of GTL+ termination resistors are not present. The Slot 1 VID lines from each of the connectors can be used to determine if a non-functional processor core or terminator card is present.

•The IOAPIC clock is T’d and distributed to the CPUs through 22 ohm series resistors.

3.3.6Slot 1 Decoupling Capacitors

•Additional VccCORE decoupling capacitance, high frequency or bulk, may be required for a properly designed Slot 1 power delivery plane and VRM. For designs utilizing a local regulator on the motherboard, adequate bulk decoupling is required. This bulk decoupling is dependent upon the regulator reaction time. Contact your regulator vendor for bulk decoupling recommendations that will meet the VRM 8.2 DC-DC Converter Specification.

•Decoupling capacitor traces should be as short and wide as possible.

3.3.7Voltage Regulator Module, VRM 8.2

•Pin A5, formerly a reserved pin, is now 12VIN.

•Pin B3, formerly a reserved pin, is now 5VIN.

•ISHARE can be used in a DP design using the same manufacturer’s VRM to share the current load between the two VRMs.

•VRM 8.2 is modified from VRM 8.1 to provide up to 18A of ICC for future processors.

•VID (voltage identification) pins from the processor will determine the VccCORE output of the VRM.

Intel®440GX AGPset Design Guide

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Contents Design Guide Intel 440GX AGPsetIntel440GX AGPset Design Guide Contents 6.5 Dimm Solution With FET SwitchesSystem Bus Clock Layout 6.3 6.482371EB PIIX4E PIIX4E Power And Ground PinsISA and X-Bus Signals Thermals / Cooling Solutions 20.1Intel440GX AGPset Platform Reference Design IntelPentiumII Processor LAI IssueFET Switches4 DIMM/FET Design Voltage Regulator Control SiliconSolution Space for Single Processor Designs With Single-End Example ATX Placement for a UP Pentium II processorExample NLX Placement for a UP Intel Pentium II processor Solution Space for Single Processor Design Based on ResultsMotherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs TablesIntel Pentium II Processor and Intel 440GX AGPset Intel Pentium II Processor and Intel 440GX AGPset 100 MHzDate Revision Description Revision HistoryIntel440GX AGPset Design Guide Introduction Page About This Design Guide IntroductionReferences Intel Pentium II Processor Intel Pentium II Processor / Intel 440GX AGPset OverviewVCR Intel 440GX AGPsetDram Interface System Bus InterfaceAccelerated Graphics Port Interface System Clocking Wired for Management InitiativePCI-to-ISA/IDE Xcelerator PIIX4E PCI InterfaceInstrumentation Remote Service BootRemote Wake-Up Power ManagementDesign Recommendations Voltage DefinitionsGeneral Design Recommendations Introduction Motherboard Design Page BGA Quadrant Assignment Major Signal Sections 82443GX Top ViewATX Form Factor NLX Form Factor Board DescriptionFour Layer Board Stack-up Routing Guidelines Single Processor Network Topology and Conditions 1 GTL+ Description2 GTL+ Layout Recommendations Single Processor DesignRecommended Trace Lengths for Single Processor Design Single Processor Recommended Trace LengthsTrace Minimum Length Maximum Length Dual Processor Recommended Trace Lengths Dual Processor SystemsSingle Processor Systems-Single-End Termination SET Dual Processor Network Topology and ConditionsSET Trace Length Requirements SET Trace Length RequirementsMinimizing Crosstalk Additional GuidelinesPractical Considerations Design Methodology 12. GTL+ Design Process Performance RequirementsRecommended 100 MHz System Flight Time Specs Topology DefinitionPre-Layout Simulation Sensitivity Analysis Simulation MethodologyPost-Layout Simulation Placement & LayoutValidation Crosstalk and the Multi-Bit Adjustment FactorFlight Time Measurement Edge Guideline @ Processor Edge Spec @ Processor Core Signal Quality MeasurementTerm Description Timing AnalysisTiming Term Value 10. Recommended 100 MHz System Timing Parameters11. Recommended 100 MHz System Flight Time Specs Timing Term Intel Pentium II Processor Intel 440GX AGPset12. Data and Associated Strobe AGP Connector Up Option Layout GuidelinesConnector AGP Layout and Routing GuidelinesWidthSpace Trace Line Length Line Length Matching 14. Control Signal Line Length RecommendationsOn-board AGP Compliant Device Down Option Layout Guidelines 13. Source Synchronous Motherboard RecommendationsCompliant 82443GX Graphics Data Routing Device 16. Control Signal Line Length Recommendations15. Source Synchronous Motherboard Recommendations 1 100 MHz 82443GX Memory Array Considerations 82443GX Memory Subsystem Layout and Routing GuidelinesTo 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs Register Data Control Clock Matching the Reference PlanesAdding Additional Decoupling Capacitor RegisterTrace Width vs. Trace Spacing Memory Layout & Routing GuidelinesSwitch 16212 Dimm Module 18. FET Switch DQ Route Example82443GX Dimm Module 82443GX 0.6 0.4 0.6 0.4 Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 20. Motherboard Model SCASA#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs21. Motherboard Model SCASB#, 4 DIMMs 23. Motherboard Model WEB#, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs24. Motherboard Model MAA140, 4 DIMMs VCC3 3 4 Dimm Routing Guidelines no FETPCI Bus Routing Guidelines 25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsHost Bridge Controller 492 BGA Decoupling Guidelines Intel 440GX AGPset Platform014 018 Clock Intel 440GX AGPset Clock Layout RecommendationsClock Routing Spacing System Bus Clock Layout440GX Ckbf Dlko PCI Clock LayoutSdram Clock Layout Net Trace Length Min Max CapNet Trace Length Min Max Card Trace AGP Clock LayoutDesign Checklist Page Pull-up and Pull-down Resistor Values OverviewSlot Connectivity Sheet 1 Intel Pentium II Processor ChecklistProcessor Pin Pin Connection Slot Connectivity Sheet 2 Slot Connectivity Sheet 3 GND & Power Pin DefinitionVtt VCC3 Reserved NC Vcc Intel Pentium II Processor Clocks Intel Pentium II Processor SignalsDesign Checklist Voltage Regulator Module, VRM Uni-Processor UP Slot 1 ChecklistDual-Processor DP Slot 1 Checklist Slot 1 Decoupling CapacitorsSEL100/66# Intel 440GX AGPset Clocks1 CK100 100 MHz Clock Synthesizer Processor Frequency SelectGcke and Dclkwr Connection Ckbf Sdram 1 to 18 Clock Buffer1 82443GX Interface 82443GX Host BridgeGX Connectivity Sheet 1 GX Connectivity Sheet 2 VTTA, Vttb 2 82443GX GTL+ Bus Interface3 82443GX PCI Interface GX Connectivity Sheet 34 82443GX AGP Interface Signal Description Register Pulled to ‘0’ Pulled to ‘1’Strapping Options Sdram Connectivity 82443GX Pins/Connection Dimm Pins Pin FunctionIntel 440GX AGPset Memory Interface Sdram ConnectionsRegistered Sdram Dimm Solution With FET SwitchesPIIX4E Connectivity Sheet 1 Signal Names Connection82371EB PIIX4E PIIX4E ConnectionsPIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 Motherboard Signal ResistorIDE Routing Guidelines CablingIDE Reset#PDD150 PDA20 Pin32,34PIIX4E Power And Ground Pins PCI Bus SignalsPIIX4E PWR & GND 11. Non-PIIX4E ISA Signals ISA SignalsISA and X-Bus Signals 10. Non-PIIX4E PCI SignalsIDE Interface USB Interface12. Non-PIIX4E IDE PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40 Flash DesignDual-Footprint Flash Design Flash Design ConsiderationsXD70 Write Protection 13. Flash Vpp RecommendationsPower Management Signals System and Test SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic Manageability Devices 18.1 Max1617 Temperature Sensor18.2 LM79 Microprocessor System Hardware Monitor Pin Number Pin Name Resistor Value Comment 18.3 82558B LOM ChecklistRequired in both a and B stepping designs USB and Multi-processor Bios Software/BIOSWake On LAN WOL Header Mechanicals Thermals / Cooling SolutionsDesign Considerations Electricals Design Consideration Layout ChecklistApplications and Add-in Hardware Routing and Board FabricationDebug Recommendations Page In-Target Probe ITP Slot 1 Test ToolsDebug/Simulation Tools Logic Analyzer Interface LAI4 I/O Buffer Models Debug FeaturesIntel Pentium II Processor LAI Issue Bus Functional Model BFM150 ohm 150 330 ohmKohm 430 ohmA20M# 150 330 ohm Debug Logic RecommendationsPICD0# 150 ohm PICD1# Design Considerations Debug ProceduresDebug Layout Debug ConsiderationsDebug Recommendations Third Party Vendors Page Supplier Contact Phone Slot 1 ConnectorProcessors GTL+ Bus Slot 1 Terminator CardsVoltage Regulator Control Silicon Vendors Voltage Regulator ModulesVoltage Regulator Control Silicon Voltage Regulator ModulesClock Drivers Power Management ComponentsFET Switches4 DIMM/FET Design Intel 440GX AGPsetOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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