Intel 440GX manual 17 82093AA Ioapic

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Design Checklist

be stubbed off the trace run and must be as close as possible to the PIIX4/PIIX4E. The capacitor must be no further than 0.5 inch from the PIIX4/PIIX4E. If a stub is required, it should be kept to a few mm maximum length. The ground connection should be made through a via to the ground plane, with no or minimal trace between the capacitor pad and the via.

Place the battery, 1K Ohm series current limit resistor, and the common-cathode isolation diode very close to the PIIX4/PIIX4E. If this is not possible, place the common-cathode diode and the 1K Ohm resistor as close to the 1uF capacitor as possible. Do not place these components between the capacitor and the PIIX4. The battery can be placed remotely from the PIIX4/PIIX4E.

On boards that have chassis-intrusion utilizing external logic powered by the VCCRTC pin, place the inverters as close to the common-cathode diode as possible. If this is not possible, keep the trace run near the center of the board.

Keep the PIIX4/PIIX4E VCCRTC trace away from the board edge. If this trace must run from opposite ends of the board, keep the trace run towards the board center, away from the board edge where contact could be made by people and equipment that handle the board.

Recommendations for Existing Board Designs to minimize ESD events that may cause loss of CMOS contents:

The effectiveness of adding a 1uF capacitor, as identified above, needs to be determined by examining the routing and placement. For example, placing the capacitor far from the PIIX4 reduces its effectiveness.

3.1782093AA (IOAPIC)

An I/O APIC is required for a DP system and is optional for a UP system.

The I/O APIC is a 5V device. All Vcc pins must be connected to 5V. Pins 19, 51 and 64 are 5V power, and pins 1, 33 and 52 are ground pins.

APICCLK may be at 2.5V, 3.3V or 5V levels. If it is shared with the Slot 1 PICCLK then it must be 2.5V. The maximum frequency is 16.666 MHz while the minimum is 14.3 MHz.

APICACK2# (pin 8) - This pin is connected to the Intel® 440GX AGPset WSC# signal.

CLK is compatible with 2.5V, 3.3V or 5V input levels. It is typically connected to the APIC clocks that are 2.5V. The maximum frequency is 33 MHz while the minimum is 25 MHz.

SMI support - The option to route SMI through the IOAPIC in a Dual-Processor system is not recommended due to timing constraints between the PIIX4E and the Slot 1 processors.

RTC Alarm Interrupt - When an IOAPIC is enabled, the IRQ8# output signal on the PIIX4E reflects the state of IRQ8. IRQ8# resides in the PIIX4E suspend well and connects to INTIN8 on the IOAPIC. If the system is put in a STD or SOFF state, the PIIX4E will continue to drive IRQ8 to the IOAPIC which could damage the IOAPIC if it is not powered. For this reason a 74LVC125 buffer is included in the schematics to isolate the IOAPIC's INTIN8 signal from the PIIX4E's IRQ8# signal when the system is suspended.

System Timer Interrupt - When an IOAPIC is enabled, the PIIX4E IRQ0 output signal reflects the state of the system timer interrupt. This signal should be connected to INTIN2 on the IOAPIC, with no pull-up.

SCI and SMB Interrupts - The IRQ9OUT# output signal on the PIIX4E reflects the state of the internally generated IRQ9 interrupt. The SCI and SMB interrupts are hardwired to IRQ9 in the

Intel®440GX AGPset Design Guide

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Contents Intel 440GX AGPset Design GuideIntel440GX AGPset Design Guide Contents Dimm Solution With FET Switches System Bus Clock Layout 6.36.4 6.5PIIX4E Power And Ground Pins ISA and X-Bus SignalsThermals / Cooling Solutions 20.1 82371EB PIIX4EIntelPentiumII Processor LAI Issue FET Switches4 DIMM/FET DesignVoltage Regulator Control Silicon Intel440GX AGPset Platform Reference DesignExample ATX Placement for a UP Pentium II processor Example NLX Placement for a UP Intel Pentium II processorSolution Space for Single Processor Design Based on Results Solution Space for Single Processor Designs With Single-EndTables Intel Pentium II Processor and Intel 440GX AGPsetIntel Pentium II Processor and Intel 440GX AGPset 100 MHz Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsRevision History Date Revision DescriptionIntel440GX AGPset Design Guide Introduction Page Introduction About This Design GuideReferences Intel Pentium II Processor / Intel 440GX AGPset Overview Intel Pentium II ProcessorIntel 440GX AGPset VCRAccelerated Graphics Port Interface System Bus InterfaceDram Interface Wired for Management Initiative PCI-to-ISA/IDE Xcelerator PIIX4EPCI Interface System ClockingRemote Service Boot InstrumentationPower Management Design RecommendationsVoltage Definitions Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page Major Signal Sections 82443GX Top View BGA Quadrant AssignmentATX Form Factor Board Description NLX Form FactorFour Layer Board Stack-up Routing Guidelines 1 GTL+ Description 2 GTL+ Layout RecommendationsSingle Processor Design Single Processor Network Topology and ConditionsTrace Minimum Length Maximum Length Single Processor Recommended Trace LengthsRecommended Trace Lengths for Single Processor Design Dual Processor Systems Single Processor Systems-Single-End Termination SETDual Processor Network Topology and Conditions Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsPractical Considerations Additional GuidelinesMinimizing Crosstalk Design Methodology Performance Requirements 12. GTL+ Design ProcessTopology Definition Pre-Layout Simulation Sensitivity AnalysisSimulation Methodology Recommended 100 MHz System Flight Time SpecsPlacement & Layout Post-Layout SimulationFlight Time Measurement Crosstalk and the Multi-Bit Adjustment FactorValidation Signal Quality Measurement Edge Guideline @ Processor Edge Spec @ Processor CoreTiming Analysis Term Description10. Recommended 100 MHz System Timing Parameters 11. Recommended 100 MHz System Flight Time SpecsTiming Term Intel Pentium II Processor Intel 440GX AGPset Timing Term ValueAGP Connector Up Option Layout Guidelines ConnectorAGP Layout and Routing Guidelines 12. Data and Associated Strobe14. Control Signal Line Length Recommendations On-board AGP Compliant Device Down Option Layout Guidelines13. Source Synchronous Motherboard Recommendations WidthSpace Trace Line Length Line Length Matching15. Source Synchronous Motherboard Recommendations 16. Control Signal Line Length RecommendationsCompliant 82443GX Graphics Data Routing Device To 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs 82443GX Memory Subsystem Layout and Routing Guidelines1 100 MHz 82443GX Memory Array Considerations Matching the Reference Planes Adding Additional Decoupling CapacitorRegister Register Data Control ClockMemory Layout & Routing Guidelines Trace Width vs. Trace Spacing18. FET Switch DQ Route Example Switch 16212 Dimm Module82443GX 0.6 0.4 0.6 0.4 Dimm Module 82443GX Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 21. Motherboard Model SCASB#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs20. Motherboard Model SCASA#, 4 DIMMs 24. Motherboard Model MAA140, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs23. Motherboard Model WEB#, 4 DIMMs 3 4 Dimm Routing Guidelines no FET PCI Bus Routing Guidelines25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs VCC3Decoupling Guidelines Intel 440GX AGPset Platform Host Bridge Controller 492 BGAIntel 440GX AGPset Clock Layout Recommendations Clock Routing SpacingSystem Bus Clock Layout 014 018 ClockPCI Clock Layout Sdram Clock LayoutNet Trace Length Min Max Cap 440GX Ckbf DlkoAGP Clock Layout Net Trace Length Min Max Card TraceDesign Checklist Page Overview Pull-up and Pull-down Resistor ValuesProcessor Pin Pin Connection Intel Pentium II Processor ChecklistSlot Connectivity Sheet 1 Slot Connectivity Sheet 2 Vtt VCC3 Reserved NC Vcc GND & Power Pin DefinitionSlot Connectivity Sheet 3 Intel Pentium II Processor Signals Intel Pentium II Processor ClocksDesign Checklist Uni-Processor UP Slot 1 Checklist Dual-Processor DP Slot 1 ChecklistSlot 1 Decoupling Capacitors Voltage Regulator Module, VRMIntel 440GX AGPset Clocks 1 CK100 100 MHz Clock SynthesizerProcessor Frequency Select SEL100/66#Ckbf Sdram 1 to 18 Clock Buffer Gcke and Dclkwr ConnectionGX Connectivity Sheet 1 82443GX Host Bridge1 82443GX Interface GX Connectivity Sheet 2 2 82443GX GTL+ Bus Interface 3 82443GX PCI InterfaceGX Connectivity Sheet 3 VTTA, VttbStrapping Options Signal Description Register Pulled to ‘0’ Pulled to ‘1’4 82443GX AGP Interface 82443GX Pins/Connection Dimm Pins Pin Function Intel 440GX AGPset Memory InterfaceSdram Connections Sdram ConnectivityDimm Solution With FET Switches Registered SdramSignal Names Connection 82371EB PIIX4EPIIX4E Connections PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 Signal Resistor IDE Routing GuidelinesCabling MotherboardReset# PDD150 PDA20Pin32,34 IDEPIIX4E PWR & GND PCI Bus SignalsPIIX4E Power And Ground Pins ISA Signals ISA and X-Bus Signals10. Non-PIIX4E PCI Signals 11. Non-PIIX4E ISA Signals12. Non-PIIX4E IDE USB InterfaceIDE Interface Flash Design Dual-Footprint Flash DesignFlash Design Considerations PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 13. Flash Vpp Recommendations Write ProtectionSystem and Test Signals Power Management SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic 18.2 LM79 Microprocessor System Hardware Monitor 18.1 Max1617 Temperature SensorManageability Devices Required in both a and B stepping designs 18.3 82558B LOM ChecklistPin Number Pin Name Resistor Value Comment Wake On LAN WOL Header Software/BIOSUSB and Multi-processor Bios Design Considerations Thermals / Cooling SolutionsMechanicals Electricals Layout Checklist Applications and Add-in HardwareRouting and Board Fabrication Design ConsiderationDebug Recommendations Page Slot 1 Test Tools Debug/Simulation ToolsLogic Analyzer Interface LAI In-Target Probe ITPDebug Features Intel Pentium II Processor LAI IssueBus Functional Model BFM 4 I/O Buffer Models150 330 ohm Kohm430 ohm 150 ohmPICD0# 150 ohm PICD1# Debug Logic RecommendationsA20M# 150 330 ohm Debug Procedures Debug LayoutDebug Considerations Design ConsiderationsDebug Recommendations Third Party Vendors Page Slot 1 Connector ProcessorsGTL+ Bus Slot 1 Terminator Cards Supplier Contact PhoneVoltage Regulator Modules Voltage Regulator Control SiliconVoltage Regulator Modules Voltage Regulator Control Silicon VendorsPower Management Components FET Switches4 DIMM/FET DesignIntel 440GX AGPset Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.