Intel 440GX manual System and Test Signals, Power Management Signals

Page 88

Design Checklist

Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop

SD[7:0]

PIIX4E

S U S A #

G P O [x]

SA[17:0]

M E M W #

M E M R #

B I O S C S #

 

SD[7:0]

+ 5 V

 

 

 

 

DQ[7:0]

 

 

 

 

V p p

N.C.

DQ[14:8]

 

 

 

 

0 . 0 1 u f

 

2/4Mbit

 

B V / B 5

 

Flash

 

 

R P #

 

V c c

 

W P #

 

 

 

 

 

SA[17:0]

V c c

 

W E #

 

0.01 uf

 

 

 

 

O E #

B Y T E #

 

 

 

C E #

 

 

3.14System and Test Signals

•8.2K ohm pull-up resistor is recommended on the TEST# pin of the PIIX4E.

3.15Power Management Signals

•A power button is required by the ACPI specification.

•PWRBTN# is connected to the front panel on/off power button. The PIIX4E integrates 16msec debouncing logic on this pin.

•All power button logic should be powered using 3VSB.

•PS_POK from the ATX connector goes to AC power loss circuitry. This circuitry allows control of whether the PIIX4E will power up after a power loss or remain off. The PIIX4E defaults to powering up the system, which may cause system model implementation issues. This circuit allows the user/BIOS to determine what will happen when a system is plugged in. See PIIX4E Application Note #7, System Power Control, for details.

•It is highly recommended that the PS_POK signal from the power supply connector not be connected directly to logic on the board without first going through a Schmitt trigger input to square-off and maintain its signal integrity.

•PS_POK logic from the power supply connector can be powered from the core voltage supply.

•RSMRST# logic should be powered by a standby supply, making sure that the input to the PIIX4E is at a 3V level. The RSMST# signal requires a minimum time delay of 1 millisecond from the rising edge of the standby power supply voltage. A Schmitt trigger circuit is recommended to drive the RSMRST# signal. To provide the required rise time, the 1 millisecond delay should be placed before the Schmitt trigger circuit. The reference design implements a 20ms delay at the input of the Schmitt trigger to ensure the Schmitt trigger inverters have sufficiently powered up before switching the input. Also ensure that voltage on RSMRST# does not exceed VCC(RTC). Refer to schematics for implementation details. If

Intel®440GX AGPset Design Guide

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Contents Intel 440GX AGPset Design GuideIntel440GX AGPset Design Guide Contents Dimm Solution With FET Switches System Bus Clock Layout 6.36.4 6.5PIIX4E Power And Ground Pins ISA and X-Bus SignalsThermals / Cooling Solutions 20.1 82371EB PIIX4EIntelPentiumII Processor LAI Issue FET Switches4 DIMM/FET DesignVoltage Regulator Control Silicon Intel440GX AGPset Platform Reference DesignExample ATX Placement for a UP Pentium II processor Example NLX Placement for a UP Intel Pentium II processorSolution Space for Single Processor Design Based on Results Solution Space for Single Processor Designs With Single-EndTables Intel Pentium II Processor and Intel 440GX AGPsetIntel Pentium II Processor and Intel 440GX AGPset 100 MHz Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsRevision History Date Revision DescriptionIntel440GX AGPset Design Guide Introduction Page Introduction About This Design GuideReferences Intel Pentium II Processor / Intel 440GX AGPset Overview Intel Pentium II ProcessorIntel 440GX AGPset VCRDram Interface System Bus InterfaceAccelerated Graphics Port Interface Wired for Management Initiative PCI-to-ISA/IDE Xcelerator PIIX4EPCI Interface System ClockingRemote Service Boot InstrumentationPower Management Design RecommendationsVoltage Definitions Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page Major Signal Sections 82443GX Top View BGA Quadrant AssignmentATX Form Factor Board Description NLX Form FactorFour Layer Board Stack-up Routing Guidelines 1 GTL+ Description 2 GTL+ Layout RecommendationsSingle Processor Design Single Processor Network Topology and ConditionsRecommended Trace Lengths for Single Processor Design Single Processor Recommended Trace LengthsTrace Minimum Length Maximum Length Dual Processor Systems Single Processor Systems-Single-End Termination SETDual Processor Network Topology and Conditions Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsMinimizing Crosstalk Additional GuidelinesPractical Considerations Design Methodology Performance Requirements 12. GTL+ Design ProcessTopology Definition Pre-Layout Simulation Sensitivity AnalysisSimulation Methodology Recommended 100 MHz System Flight Time SpecsPlacement & Layout Post-Layout SimulationValidation Crosstalk and the Multi-Bit Adjustment FactorFlight Time Measurement Signal Quality Measurement Edge Guideline @ Processor Edge Spec @ Processor CoreTiming Analysis Term Description10. Recommended 100 MHz System Timing Parameters 11. Recommended 100 MHz System Flight Time SpecsTiming Term Intel Pentium II Processor Intel 440GX AGPset Timing Term ValueAGP Connector Up Option Layout Guidelines ConnectorAGP Layout and Routing Guidelines 12. Data and Associated Strobe14. Control Signal Line Length Recommendations On-board AGP Compliant Device Down Option Layout Guidelines13. Source Synchronous Motherboard Recommendations WidthSpace Trace Line Length Line Length MatchingCompliant 82443GX Graphics Data Routing Device 16. Control Signal Line Length Recommendations15. Source Synchronous Motherboard Recommendations 1 100 MHz 82443GX Memory Array Considerations 82443GX Memory Subsystem Layout and Routing GuidelinesTo 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs Matching the Reference Planes Adding Additional Decoupling CapacitorRegister Register Data Control ClockMemory Layout & Routing Guidelines Trace Width vs. Trace Spacing18. FET Switch DQ Route Example Switch 16212 Dimm Module82443GX 0.6 0.4 0.6 0.4 Dimm Module 82443GX Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 20. Motherboard Model SCASA#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs21. Motherboard Model SCASB#, 4 DIMMs 23. Motherboard Model WEB#, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs24. Motherboard Model MAA140, 4 DIMMs 3 4 Dimm Routing Guidelines no FET PCI Bus Routing Guidelines25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs VCC3Decoupling Guidelines Intel 440GX AGPset Platform Host Bridge Controller 492 BGAIntel 440GX AGPset Clock Layout Recommendations Clock Routing SpacingSystem Bus Clock Layout 014 018 ClockPCI Clock Layout Sdram Clock LayoutNet Trace Length Min Max Cap 440GX Ckbf DlkoAGP Clock Layout Net Trace Length Min Max Card TraceDesign Checklist Page Overview Pull-up and Pull-down Resistor ValuesSlot Connectivity Sheet 1 Intel Pentium II Processor ChecklistProcessor Pin Pin Connection Slot Connectivity Sheet 2 Slot Connectivity Sheet 3 GND & Power Pin DefinitionVtt VCC3 Reserved NC Vcc Intel Pentium II Processor Signals Intel Pentium II Processor ClocksDesign Checklist Uni-Processor UP Slot 1 Checklist Dual-Processor DP Slot 1 ChecklistSlot 1 Decoupling Capacitors Voltage Regulator Module, VRMIntel 440GX AGPset Clocks 1 CK100 100 MHz Clock SynthesizerProcessor Frequency Select SEL100/66#Ckbf Sdram 1 to 18 Clock Buffer Gcke and Dclkwr Connection1 82443GX Interface 82443GX Host BridgeGX Connectivity Sheet 1 GX Connectivity Sheet 2 2 82443GX GTL+ Bus Interface 3 82443GX PCI InterfaceGX Connectivity Sheet 3 VTTA, Vttb4 82443GX AGP Interface Signal Description Register Pulled to ‘0’ Pulled to ‘1’Strapping Options 82443GX Pins/Connection Dimm Pins Pin Function Intel 440GX AGPset Memory InterfaceSdram Connections Sdram ConnectivityDimm Solution With FET Switches Registered SdramSignal Names Connection 82371EB PIIX4EPIIX4E Connections PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 Signal Resistor IDE Routing GuidelinesCabling MotherboardReset# PDD150 PDA20Pin32,34 IDEPIIX4E Power And Ground Pins PCI Bus SignalsPIIX4E PWR & GND ISA Signals ISA and X-Bus Signals10. Non-PIIX4E PCI Signals 11. Non-PIIX4E ISA SignalsIDE Interface USB Interface12. Non-PIIX4E IDE Flash Design Dual-Footprint Flash DesignFlash Design Considerations PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 13. Flash Vpp Recommendations Write ProtectionSystem and Test Signals Power Management SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic Manageability Devices 18.1 Max1617 Temperature Sensor18.2 LM79 Microprocessor System Hardware Monitor Pin Number Pin Name Resistor Value Comment 18.3 82558B LOM ChecklistRequired in both a and B stepping designs USB and Multi-processor Bios Software/BIOSWake On LAN WOL Header Mechanicals Thermals / Cooling SolutionsDesign Considerations Electricals Layout Checklist Applications and Add-in HardwareRouting and Board Fabrication Design ConsiderationDebug Recommendations Page Slot 1 Test Tools Debug/Simulation ToolsLogic Analyzer Interface LAI In-Target Probe ITPDebug Features Intel Pentium II Processor LAI IssueBus Functional Model BFM 4 I/O Buffer Models150 330 ohm Kohm430 ohm 150 ohmA20M# 150 330 ohm Debug Logic RecommendationsPICD0# 150 ohm PICD1# Debug Procedures Debug LayoutDebug Considerations Design ConsiderationsDebug Recommendations Third Party Vendors Page Slot 1 Connector ProcessorsGTL+ Bus Slot 1 Terminator Cards Supplier Contact PhoneVoltage Regulator Modules Voltage Regulator Control SiliconVoltage Regulator Modules Voltage Regulator Control Silicon VendorsPower Management Components FET Switches4 DIMM/FET DesignIntel 440GX AGPset Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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