Intel 440GX manual Design Checklist

Page 66

Design Checklist

used by other logic requiring CMOS/TTL logic levels. The VID lines on the Slot 1 connector are 5V tolerant.

•Vcc (±5%) should be provided to the Slot 1 signal Vcc pin B109. This power connection is not used by the Intel® Pentium® II processor. It is required for the Slot 1 EMT tool and may be required by future Boxed processors.

•The JTAG port must be properly terminated even if it is not used. See the Debug Recommendations for further information that may affect these resistor values.

•The EMI pins of the Slot 1 connector (pins B1, B41, B61, B81 and B100) should be connected to system or chassis ground through zero ohm resistors. The determination to install these resistors is design dependent and can be determined through empirical methods.

•TRST# must be driven low during reset to all components with TRST# pins. Connecting a pull-down resistor to TRST# will accomplish the reset of the port.

•If two Vtt regulators are used, one at each end of the bus, Intel recommends connecting the two regulator outputs together with a wide trace that runs the along the same basic path as the

GTL+ signals (beware of crosstalk). VREF should be generated at each AGPset component from this combined VTT. This is simply a recommendation to minimize the effects of noise. See AP-523 Intel® Pentium® Pro Processor Power Distribution Guidelines for more information.

•A single VTT regulator may be used. For a UP system a simplistic calculation for maximum worst case current is 5.0A. This takes into consideration that some signals are not used by the Intel® 440GX AGPset.

•Motherboards planning to support the Boxed Intel® Pentium® II processor must provide a matched power header for the Boxed Intel® Pentium® II processor fan/heatsink power cable connector. The power header must be positioned within close proximity to the Slot 1 connector.

•The Slot 1 connector signal SLOTOCC# (Pin B101) is a ground on the Slot 1 processor. The presence of a CPU core can be determined from a combination of non-zero VID signals, (all ones designates “No Core”) and if the state of SLOTOCC# is low.

•ITPREQ[1:0]#, ITPRDY[1:0]# can individually be hooked to either CPU. The ITP .inf file must match the connections.

•DBRESET (ITP Reset signal) requires a 240 ohm pull-up to VCC3.

Intel®440GX AGPset Design Guide

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Contents Intel 440GX AGPset Design GuideIntel440GX AGPset Design Guide Contents 6.4 Dimm Solution With FET SwitchesSystem Bus Clock Layout 6.3 6.5Thermals / Cooling Solutions 20.1 PIIX4E Power And Ground PinsISA and X-Bus Signals 82371EB PIIX4EVoltage Regulator Control Silicon IntelPentiumII Processor LAI IssueFET Switches4 DIMM/FET Design Intel440GX AGPset Platform Reference DesignSolution Space for Single Processor Design Based on Results Example ATX Placement for a UP Pentium II processorExample NLX Placement for a UP Intel Pentium II processor Solution Space for Single Processor Designs With Single-EndIntel Pentium II Processor and Intel 440GX AGPset 100 MHz TablesIntel Pentium II Processor and Intel 440GX AGPset Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsRevision History Date Revision DescriptionIntel440GX AGPset Design Guide Introduction Page Introduction About This Design GuideReferences Intel Pentium II Processor / Intel 440GX AGPset Overview Intel Pentium II ProcessorIntel 440GX AGPset VCRSystem Bus Interface Dram InterfaceAccelerated Graphics Port Interface PCI Interface Wired for Management InitiativePCI-to-ISA/IDE Xcelerator PIIX4E System ClockingRemote Service Boot InstrumentationVoltage Definitions Power ManagementDesign Recommendations Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page Major Signal Sections 82443GX Top View BGA Quadrant AssignmentATX Form Factor Board Description NLX Form FactorFour Layer Board Stack-up Routing Guidelines Single Processor Design 1 GTL+ Description2 GTL+ Layout Recommendations Single Processor Network Topology and ConditionsSingle Processor Recommended Trace Lengths Recommended Trace Lengths for Single Processor DesignTrace Minimum Length Maximum Length Dual Processor Network Topology and Conditions Dual Processor SystemsSingle Processor Systems-Single-End Termination SET Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsAdditional Guidelines Minimizing CrosstalkPractical Considerations Design Methodology Performance Requirements 12. GTL+ Design ProcessSimulation Methodology Topology DefinitionPre-Layout Simulation Sensitivity Analysis Recommended 100 MHz System Flight Time SpecsPlacement & Layout Post-Layout SimulationCrosstalk and the Multi-Bit Adjustment Factor ValidationFlight Time Measurement Signal Quality Measurement Edge Guideline @ Processor Edge Spec @ Processor CoreTiming Analysis Term DescriptionTiming Term Intel Pentium II Processor Intel 440GX AGPset 10. Recommended 100 MHz System Timing Parameters11. Recommended 100 MHz System Flight Time Specs Timing Term ValueAGP Layout and Routing Guidelines AGP Connector Up Option Layout GuidelinesConnector 12. Data and Associated Strobe13. Source Synchronous Motherboard Recommendations 14. Control Signal Line Length RecommendationsOn-board AGP Compliant Device Down Option Layout Guidelines WidthSpace Trace Line Length Line Length Matching16. Control Signal Line Length Recommendations Compliant 82443GX Graphics Data Routing Device15. Source Synchronous Motherboard Recommendations 82443GX Memory Subsystem Layout and Routing Guidelines 1 100 MHz 82443GX Memory Array ConsiderationsTo 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs Register Matching the Reference PlanesAdding Additional Decoupling Capacitor Register Data Control ClockMemory Layout & Routing Guidelines Trace Width vs. Trace Spacing18. FET Switch DQ Route Example Switch 16212 Dimm Module82443GX 0.6 0.4 0.6 0.4 Dimm Module 82443GX Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs 20. Motherboard Model SCASA#, 4 DIMMs21. Motherboard Model SCASB#, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs 23. Motherboard Model WEB#, 4 DIMMs24. Motherboard Model MAA140, 4 DIMMs 25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs 3 4 Dimm Routing Guidelines no FETPCI Bus Routing Guidelines VCC3Decoupling Guidelines Intel 440GX AGPset Platform Host Bridge Controller 492 BGASystem Bus Clock Layout Intel 440GX AGPset Clock Layout RecommendationsClock Routing Spacing 014 018 ClockNet Trace Length Min Max Cap PCI Clock LayoutSdram Clock Layout 440GX Ckbf DlkoAGP Clock Layout Net Trace Length Min Max Card TraceDesign Checklist Page Overview Pull-up and Pull-down Resistor ValuesIntel Pentium II Processor Checklist Slot Connectivity Sheet 1Processor Pin Pin Connection Slot Connectivity Sheet 2 GND & Power Pin Definition Slot Connectivity Sheet 3Vtt VCC3 Reserved NC Vcc Intel Pentium II Processor Signals Intel Pentium II Processor ClocksDesign Checklist Slot 1 Decoupling Capacitors Uni-Processor UP Slot 1 ChecklistDual-Processor DP Slot 1 Checklist Voltage Regulator Module, VRMProcessor Frequency Select Intel 440GX AGPset Clocks1 CK100 100 MHz Clock Synthesizer SEL100/66#Ckbf Sdram 1 to 18 Clock Buffer Gcke and Dclkwr Connection82443GX Host Bridge 1 82443GX InterfaceGX Connectivity Sheet 1 GX Connectivity Sheet 2 GX Connectivity Sheet 3 2 82443GX GTL+ Bus Interface3 82443GX PCI Interface VTTA, VttbSignal Description Register Pulled to ‘0’ Pulled to ‘1’ 4 82443GX AGP InterfaceStrapping Options Sdram Connections 82443GX Pins/Connection Dimm Pins Pin FunctionIntel 440GX AGPset Memory Interface Sdram ConnectivityDimm Solution With FET Switches Registered SdramPIIX4E Connections Signal Names Connection82371EB PIIX4E PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 Cabling Signal ResistorIDE Routing Guidelines MotherboardPin32,34 Reset#PDD150 PDA20 IDEPCI Bus Signals PIIX4E Power And Ground PinsPIIX4E PWR & GND 10. Non-PIIX4E PCI Signals ISA SignalsISA and X-Bus Signals 11. Non-PIIX4E ISA SignalsUSB Interface IDE Interface12. Non-PIIX4E IDE Flash Design Considerations Flash DesignDual-Footprint Flash Design PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 13. Flash Vpp Recommendations Write ProtectionSystem and Test Signals Power Management SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic 18.1 Max1617 Temperature Sensor Manageability Devices18.2 LM79 Microprocessor System Hardware Monitor 18.3 82558B LOM Checklist Pin Number Pin Name Resistor Value CommentRequired in both a and B stepping designs Software/BIOS USB and Multi-processor BiosWake On LAN WOL Header Thermals / Cooling Solutions MechanicalsDesign Considerations Electricals Routing and Board Fabrication Layout ChecklistApplications and Add-in Hardware Design ConsiderationDebug Recommendations Page Logic Analyzer Interface LAI Slot 1 Test ToolsDebug/Simulation Tools In-Target Probe ITPBus Functional Model BFM Debug FeaturesIntel Pentium II Processor LAI Issue 4 I/O Buffer Models430 ohm 150 330 ohmKohm 150 ohmDebug Logic Recommendations A20M# 150 330 ohmPICD0# 150 ohm PICD1# Debug Considerations Debug ProceduresDebug Layout Design ConsiderationsDebug Recommendations Third Party Vendors Page GTL+ Bus Slot 1 Terminator Cards Slot 1 ConnectorProcessors Supplier Contact PhoneVoltage Regulator Modules Voltage Regulator ModulesVoltage Regulator Control Silicon Voltage Regulator Control Silicon VendorsIntel 440GX AGPset Power Management ComponentsFET Switches4 DIMM/FET Design Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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