Intel 440GX manual 4 82443GX AGP Interface, Strapping Options

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Design Checklist

—TMS (connector pin A3) and TDI (connector pin A4) should be independently bussed and pulled up with 5K ohm (approximate) resistors.

—TRST# (connector pin A1) and TCK (connector pin B2) should be independently bussed and pulled down with 5K ohm (approximate) resistors.

—TDO (connector pin B4) should be left open.

3.5.482443GX AGP Interface

•The following will help reduce the AGPREF margin needed when data is being written or read via the AGP bus interface.

—Use only two 1% resistors for the AGPREF voltage divider on the 82443GX boards. This will limit the AGPREF margin needed to 100mV below 40% of Vcc. If 5% resistors are used, the AGPREF margin needed would be 160mV.

—Have “at least” 2x spacing around Strobe A and B to decrease crosstalk inductive coupling from adjacent GAD signals. This could reduce crosstalk by as much as 100-300 mV.

•The AGP interface is designed for a 3.3V operating environment, and both the master and target AGP compliant devices must be driven by the same supply line.

•No external termination for signal quality is required by the AGP spec., but can be added to improve signal integrity provided the timing constraints are still satisfied.

•AGP interrupts may be shared with PCI interrupts similar to the recommendations in the PCI 2.1 spec. For example, in a system with 3 PCI slots and one AGP slot, interrupts should be connected such that each of the four INTA# lines hooks to a unique input on the PIIX4E. It is recommended that the interrupts be staggered. It is also recommended that each PIRQ be programmed to a different IRQ if possible.

•It is the requirement of the motherboard designer to properly interface the AGP interrupts to the PCI bus. In this reference design, the AGP interrupts are pulled up to 3.3V, and a buffer is used to isolate the 5V environment from the AGP bus.

•To minimize the impact of any mismatch between the motherboard and the add-in card, a board impedance of 65 ±15 ohms is strongly recommended.

•At each component that requires it, AGP_Vref should be generated locally from the AGP interface Vddq rail.

Table 3-5. Strapping Options

Signal

Description

Register

Pulled to ‘0’

Pulled to ‘1’

 

 

 

 

 

MAB9#

AGP Signals

PMCR[1]

AGP Enabled (Default)

AGP Disabled

 

 

 

 

 

MAB11#

In Order Queue

MGXCFG[2]

Non-Pipelined

Maximum Queue Depth

Depth

Enabled (Default)

 

 

 

 

 

 

 

 

MAB12#

Host Frequency

NGXCFG[13]

Reserved

100MHz (Default)

 

 

 

 

 

NOTES:

1.MAB[9]# is connected to internal 50K ohm pull-down resistors. MAB[12:11] are connected to internal 50K ohm pull-up resistors.

2.Note that strapping signals are not driven by the 82443GX during reset sequence. Proper strapping must be used to define logical values for these signals. Default values provided by the internal pull-up or pull-down resistors can be overridden by an external resistor.

3.When AGP is disabled, all AGP signals are tri-stated and isolated. They do not need external pull-up resistors. The AGP signals are PIPE#, SBA[7:0], RBF#, ST[2:0], GADSTBA, GADSTBB, SBSTB, GFRAME#, GIRDY#, GTRDY#, GSTOP#, GDEVSEL#, GREQ#, GGNT#, GAD[31:0], FC/BE[3:0]#, GPAR.

4.When AGP is disabled, tie AGP_Vref to ground.

Intel®440GX AGPset Design Guide

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Contents Design Guide Intel 440GX AGPsetIntel440GX AGPset Design Guide Contents System Bus Clock Layout 6.3 Dimm Solution With FET Switches6.4 6.5ISA and X-Bus Signals PIIX4E Power And Ground PinsThermals / Cooling Solutions 20.1 82371EB PIIX4EFET Switches4 DIMM/FET Design IntelPentiumII Processor LAI IssueVoltage Regulator Control Silicon Intel440GX AGPset Platform Reference DesignExample NLX Placement for a UP Intel Pentium II processor Example ATX Placement for a UP Pentium II processorSolution Space for Single Processor Design Based on Results Solution Space for Single Processor Designs With Single-EndIntel Pentium II Processor and Intel 440GX AGPset TablesIntel Pentium II Processor and Intel 440GX AGPset 100 MHz Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMsDate Revision Description Revision HistoryIntel440GX AGPset Design Guide Introduction Page About This Design Guide IntroductionReferences Intel Pentium II Processor Intel Pentium II Processor / Intel 440GX AGPset OverviewVCR Intel 440GX AGPsetDram Interface System Bus InterfaceAccelerated Graphics Port Interface PCI-to-ISA/IDE Xcelerator PIIX4E Wired for Management InitiativePCI Interface System ClockingInstrumentation Remote Service BootDesign Recommendations Power ManagementVoltage Definitions Remote Wake-UpGeneral Design Recommendations Introduction Motherboard Design Page BGA Quadrant Assignment Major Signal Sections 82443GX Top ViewATX Form Factor NLX Form Factor Board DescriptionFour Layer Board Stack-up Routing Guidelines 2 GTL+ Layout Recommendations 1 GTL+ DescriptionSingle Processor Design Single Processor Network Topology and ConditionsRecommended Trace Lengths for Single Processor Design Single Processor Recommended Trace LengthsTrace Minimum Length Maximum Length Single Processor Systems-Single-End Termination SET Dual Processor SystemsDual Processor Network Topology and Conditions Dual Processor Recommended Trace LengthsSET Trace Length Requirements SET Trace Length RequirementsMinimizing Crosstalk Additional GuidelinesPractical Considerations Design Methodology 12. GTL+ Design Process Performance RequirementsPre-Layout Simulation Sensitivity Analysis Topology DefinitionSimulation Methodology Recommended 100 MHz System Flight Time SpecsPost-Layout Simulation Placement & LayoutValidation Crosstalk and the Multi-Bit Adjustment FactorFlight Time Measurement Edge Guideline @ Processor Edge Spec @ Processor Core Signal Quality MeasurementTerm Description Timing Analysis11. Recommended 100 MHz System Flight Time Specs 10. Recommended 100 MHz System Timing ParametersTiming Term Intel Pentium II Processor Intel 440GX AGPset Timing Term ValueConnector AGP Connector Up Option Layout GuidelinesAGP Layout and Routing Guidelines 12. Data and Associated StrobeOn-board AGP Compliant Device Down Option Layout Guidelines 14. Control Signal Line Length Recommendations13. Source Synchronous Motherboard Recommendations WidthSpace Trace Line Length Line Length MatchingCompliant 82443GX Graphics Data Routing Device 16. Control Signal Line Length Recommendations15. Source Synchronous Motherboard Recommendations 1 100 MHz 82443GX Memory Array Considerations 82443GX Memory Subsystem Layout and Routing GuidelinesTo 82443GX MDs & MECCs To DIMM10 DQs To DIMM32 DQs Adding Additional Decoupling Capacitor Matching the Reference PlanesRegister Register Data Control ClockTrace Width vs. Trace Spacing Memory Layout & Routing GuidelinesSwitch 16212 Dimm Module 18. FET Switch DQ Route Example82443GX Dimm Module 82443GX 0.6 0.4 0.6 0.4 Dimm Module24. Motherboard Model-DQMB1,5, 4 DIMMs 20. Motherboard Model SCASA#, 4 DIMMs 19. Motherboard Model SRASB#, 4 DIMMs21. Motherboard Model SCASB#, 4 DIMMs 23. Motherboard Model WEB#, 4 DIMMs 22. Motherboard Model WEA#, 4 DIMMs24. Motherboard Model MAA140, 4 DIMMs PCI Bus Routing Guidelines 3 4 Dimm Routing Guidelines no FET25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs VCC3Host Bridge Controller 492 BGA Decoupling Guidelines Intel 440GX AGPset PlatformClock Routing Spacing Intel 440GX AGPset Clock Layout RecommendationsSystem Bus Clock Layout 014 018 ClockSdram Clock Layout PCI Clock LayoutNet Trace Length Min Max Cap 440GX Ckbf DlkoNet Trace Length Min Max Card Trace AGP Clock LayoutDesign Checklist Page Pull-up and Pull-down Resistor Values OverviewSlot Connectivity Sheet 1 Intel Pentium II Processor ChecklistProcessor Pin Pin Connection Slot Connectivity Sheet 2 Slot Connectivity Sheet 3 GND & Power Pin DefinitionVtt VCC3 Reserved NC Vcc Intel Pentium II Processor Clocks Intel Pentium II Processor SignalsDesign Checklist Dual-Processor DP Slot 1 Checklist Uni-Processor UP Slot 1 ChecklistSlot 1 Decoupling Capacitors Voltage Regulator Module, VRM1 CK100 100 MHz Clock Synthesizer Intel 440GX AGPset ClocksProcessor Frequency Select SEL100/66#Gcke and Dclkwr Connection Ckbf Sdram 1 to 18 Clock Buffer1 82443GX Interface 82443GX Host BridgeGX Connectivity Sheet 1 GX Connectivity Sheet 2 3 82443GX PCI Interface 2 82443GX GTL+ Bus InterfaceGX Connectivity Sheet 3 VTTA, Vttb4 82443GX AGP Interface Signal Description Register Pulled to ‘0’ Pulled to ‘1’Strapping Options Intel 440GX AGPset Memory Interface 82443GX Pins/Connection Dimm Pins Pin FunctionSdram Connections Sdram ConnectivityRegistered Sdram Dimm Solution With FET Switches82371EB PIIX4E Signal Names ConnectionPIIX4E Connections PIIX4E Connectivity Sheet 1PIIX4E Connectivity Sheet 2 PIIX4E Connectivity Sheet 3 PIIX4E Connectivity Sheet 4 IDE Routing Guidelines Signal ResistorCabling MotherboardPDD150 PDA20 Reset#Pin32,34 IDEPIIX4E Power And Ground Pins PCI Bus SignalsPIIX4E PWR & GND ISA and X-Bus Signals ISA Signals10. Non-PIIX4E PCI Signals 11. Non-PIIX4E ISA SignalsIDE Interface USB Interface12. Non-PIIX4E IDE Dual-Footprint Flash Design Flash DesignFlash Design Considerations PLCC32 to TSOP40 PLCC32 to PSOP44 PDIP32 to TDIP40XD70 Write Protection 13. Flash Vpp RecommendationsPower Management Signals System and Test SignalsVCC3 Power Button Implementation Miscellaneous 17 82093AA Ioapic Manageability Devices 18.1 Max1617 Temperature Sensor18.2 LM79 Microprocessor System Hardware Monitor Pin Number Pin Name Resistor Value Comment 18.3 82558B LOM ChecklistRequired in both a and B stepping designs USB and Multi-processor Bios Software/BIOSWake On LAN WOL Header Mechanicals Thermals / Cooling SolutionsDesign Considerations Electricals Applications and Add-in Hardware Layout ChecklistRouting and Board Fabrication Design ConsiderationDebug Recommendations Page Debug/Simulation Tools Slot 1 Test ToolsLogic Analyzer Interface LAI In-Target Probe ITPIntel Pentium II Processor LAI Issue Debug FeaturesBus Functional Model BFM 4 I/O Buffer ModelsKohm 150 330 ohm430 ohm 150 ohmA20M# 150 330 ohm Debug Logic RecommendationsPICD0# 150 ohm PICD1# Debug Layout Debug ProceduresDebug Considerations Design ConsiderationsDebug Recommendations Third Party Vendors Page Processors Slot 1 ConnectorGTL+ Bus Slot 1 Terminator Cards Supplier Contact PhoneVoltage Regulator Control Silicon Voltage Regulator ModulesVoltage Regulator Modules Voltage Regulator Control Silicon VendorsFET Switches4 DIMM/FET Design Power Management ComponentsIntel 440GX AGPset Clock DriversOther Processor Components Reference Design Schematics Page Intel 440GX AGPset Platform Reference Design 82443GX Component System bus and Dram Interfaces VRM Power Connectors Front Panel Jumpers

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
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