Agilent Technologies user manual FS2010 Software and Timing mode

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The ADDR, ADDR_B and DATA variables

FS2010 Software and Timing mode

The FS2010 Decoder should NOT be run when the logic analyzer is configured in timing mode. This will cause the system to hang.

The ADDR and DATA variables in the FORMAT menu are assigned to the AD[31:0] signals on the PCI-X bus. The ADDR_B is the AD[63:32] signals on the PCI-X bus.

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Contents Page FS2010 Software and Timing mode J2 Signal Connector How to reach us Product Warranty Limitation WarrantyAssistance How to Use This Manual IntroductionAccessories Supplied Analyzing the PCI-X Local BusPage Configuration Files Connecting the 167xx Agilent logic analyzer to the FS2010 How to install a PCI-X add-in card into the FS2010Setting up the 167xx Analyzer 167xx Licensing 1680/90/900 Licensing Offline Analysis Page Page Format Menu PCI-X Transaction Decode Software FS2010 Software and Timing mode Cycle variable DEVSEL# TRDY# STOP# State Analysis Acquiring DataConfiguring the Workspace for PCI-X Analysis State Listing Display Above figure shows the listing from the 169xx frame Functionality FS2010 Transaction Decode Software Name Base DescriptionTiming Analysis Waveform Display Use of EyeFinder/Eyescan Transaction Viewer Characteristics General InformationSignal Connections State/Timing Adapter Probe interface pinoutJ2 Signal Connector INTD# J3 Signal Connections SERR# J4 Signal Connections Samtec