Texas Instruments TMS320DM647 manual Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram

Page 20

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Peripheral Architecture

SDCFG Bit

 

 

 

 

 

 

Logical Address

 

 

 

 

 

 

IBANK

PAGESIZE

31:28

27

26

25

24

23

22:17

16

15

14

13

12

11

10

9:2

0

0

X

X

X

X

X

 

 

 

 

nrb=14(1)

 

 

 

 

ncb=8

1

0

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1 ncb=8

2

0

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=2

ncb=8

3

0

X

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

ncb=8

0

1

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=9

1

1

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

ncb=9

2

1

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

ncb=9

3

1

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

 

ncb=9

0

2

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=10

1

2

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

ncb=10

2

2

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

ncb=10

3

2

X

 

 

 

 

nrb=13

 

 

 

 

nbb=3

 

 

ncb=10

0

3

X

X

 

 

 

 

nrb=14

 

 

 

 

 

 

ncb=11

 

1

3

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

 

ncb=11

 

2

3

X

 

 

 

 

nrb=12

 

 

 

nbb=2

 

 

ncb=11

 

3

3

X

 

 

 

nrb=11

 

 

 

nbb=3

 

 

 

ncb=11

 

(1)Legend: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits; BE = byte enable bits.

Figure 12. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM

SDCFG Bit

 

 

 

 

 

 

 

Logical Address

 

 

 

 

 

 

 

IBANK

PAGESIZE

31:28

27

26

25

24

23

22

21:16

15

14

13

12

11

10

9

8:1

0

0

X

X

X

X

X

X

 

 

 

 

nrb=14(1)

 

 

 

 

ncb=8

1

0

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1 ncb=8

2

0

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

ncb=8

3

0

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=3

 

ncb=8

0

1

X

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=9

1

1

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

ncb=9

2

1

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

ncb=9

3

1

X

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

 

ncb=9

0

2

X

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=10

1

2

X

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

ncb=10

2

2

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=2

 

ncb=10

3

2

X

 

 

 

 

nrb=14

 

 

 

 

 

nbb=3

 

 

ncb=10

0

3

X

X

X

 

 

 

 

nrb=14

 

 

 

 

 

ncb=11

 

1

3

X

X

 

 

 

 

nrb=14

 

 

 

 

nbb=1

 

ncb=11

 

2

3

X

 

 

 

 

nrb=13

 

 

 

 

nbb=2

 

ncb=11

 

3

3

X

 

 

 

 

nrb=12

 

 

 

 

nbb=3

 

 

ncb=11

 

(1)Legend: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits; BE = byte enable bit.

20

DSP DDR2 Memory Controller

SPRUEK5A –October 2007

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Image 20
Page 19 Page 21
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandWrite WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable BytesBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionReset Sources Self-Refresh ModeReset Considerations 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function SelectionDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl ReseTable A-1. Document Revision History Additions/Modifications/DeletionsRfid Products ApplicationsDSP
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