Texas Instruments TMS320DM647, DM648 DSP DDR2 Memory Refresh Specification, Sdrfc Configuration

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Using the DDR2 Memory Controller

Table 12 displays the DDR2-533 refresh rate specification.

Table 12. DDR2 Memory Refresh Specification

Symbol	Description	Value
tREF	Average Periodic Refresh Interval	7.8 μs

Therefore, the value for the REFRESH-RATE can be calculated as follows:

REFRESH_RATE = 266.5 MHz × 7.8 μs = 2078.7 = 81Eh

Table 13 shows the resulting SDRFC configuration.

		Table 13. SDRFC Configuration
Field	Value	Function Selection
SR	0	DDR2 memory controller is not in self-refresh mode.
REFRESH_RATE	81Eh	Set to 81Eh DDR2 clock cycles to meet the DDR2 memory refresh rate
		requirement.

3.2.3Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)

The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 14 and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along with the data sheet value. These tables also provide a formula to calculate the register field value and displays the resulting calculation. Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1. See Section 4.5 and Section 4.6 for more information.

Table 14. SDTIM1 Configuration

	DDR2 SDRAM
	Data Sheet
Register	Parameter		Data Sheet	Formula (Register Field	Field
Field Name	Name	Description	Value (nS)	Must Be ≥)	Value
T_RFC	tRFC	Refresh cycle time	127.5	(tRFC × fDDR2_CLK) - 1	33
T_RP	tRP	Precharge command to refresh or	15	(tRP × fDDR2_CLK) - 1	3
		activate command
T_RCD	tRCD	Activate command to read/write	15	(tRCD × fDDR2_CLK) - 1	3
		command
T_WR	tWR	Write recovery time	15	(tWR × fDDR2_CLK) - 1	3
T_RAS	tRAS	Active to precharge command	40	(tRAC × fDDR2_CLK) - 1	10
T_RC	tRC	Activate to Activate command in the	55	(tRC × fDDR2_CLK) - 1	14
		same bank
T_RRD	tRRD	Activate to Activate command in a	10	(tRRD × fDDR2_CLK) - 1	3
		different bank
T_WTR	tWTR	Write to read command delay	7.5	(tWTR × fDDR2_CLK) - 1	1

34	DSP DDR2 Memory Controller	SPRUEK5A –October 2007
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable BytesBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionReset Considerations Self-Refresh ModeReset Sources DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory InitializationInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function SelectionConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl ReseTable A-1. Document Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid