Texas Instruments TMS320DM647, DM648 DSP manual List of Figures

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	List of Figures
1	DDR2 Memory Controller Block Diagram	10
2	DDR2 Memory Controller Signals	12
3	DDR2 MRS and EMRS Command	14
4	Refresh Command	15
5	ACTV Command	15
6	DCAB Command	16
7	DEAC Command	16
8	DDR2 READ Command	17
9	DDR2 WRT Command	18
10	Byte Alignment	19
11	Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM	19
12	Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM	20
13	Logical Address-to-DDR2 SDRAM Address Map	21
14	DDR2 SDRAM Column, Row, and Bank Access	22
15	DDR2 Memory Controller FIFO Block Diagram	23
16	DDR2 Memory Controller Reset Block Diagram	26
17	Connecting to Two 16-Bit DDR2 SDRAM Devices	30
18	Connecting to a Single 16-Bit DDR2 SDRAM Device	31
19	Connecting to Two 8-Bit DDR2 SDRAM Devices	32
20	Module ID and Revision Register (MIDR)	37
21	DDR2 Memory Controller Status Register (DMCSTAT)	37
22	SDRAM Configuration Register (SDCFG)	38
23	SDRAM Refresh Control Register (SDRFC)	40
24	SDRAM Timing 1 Register (SDTIM1)	41
25	SDRAM Timing 2 Register (SDTIM2)	43
26	Burst Priority Register (BPRIO)	44
27	DDR2 Memory Controller Control Register (DMCCTL)	45

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List of Figures

SPRUEK5A –October 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin DescriptionDDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol DescriptionsMode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandWrite WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable BytesBank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeReset Sources 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function SelectionDDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationSDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsSdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl ReseTable A-1. Document Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid