Texas Instruments DM648 DSP manual Programming the Sdram Configuration Register Sdcfg, Timunlock

Page 33

www.ti.com

Using the DDR2 Memory Controller

3.2Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications

The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By programming the SDRAM Configuration Register (SDCFG), SDRAM Refresh Control Register (SDRFC), SDRAM Timing 1 Register (SDTIM1), and SDRAM Timing 2 Register (SDTIM2), the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D-2A compliant DDR2 SDRAM devices.

As an example, the following sections describe how to configure each of these registers for access to two 1Gb, 16-bit wide DDR2 SDRAM devices connected as shown on Figure 17, where each device has the following configuration:

∙Maximum data rate: 533MHz

∙Number of banks: 8

∙Page size: 1024 words

∙CAS latency: 4

It is assumed that the frequency of the DDR2 memory controller clock (DDR_CLK) is set to 266.5MHz.

3.2.1Programming the SDRAM Configuration Register (SDCFG)

The SDRAM configuration register (SDCFG) contains register fields that configure the DDR2 memory controller to match the data bus width, CAS latency, number of banks, and page size of the attached DDR2 memory.

Table 11 shows the resulting SDCFG configuration. Note that the value of the TIMUNLOCK field is dependent on whether or not it is desirable to unlock SDTIM1 and SDTIM2. The TIMUNLOCK bit should only be set to 1 when the SDTIM1 and SDTIM2 needs to be updated.

 

 

Table 11. SDCFG Configuration

Field

Value

Function Selection

TIMUNLOCK

x

Set to 1 to unlock the SDRAM timing and timing 2 registers. Cleared to 0 to lock the SDRAM

 

 

timing and timing 2 registers.

NM

0h

To configure the DDR2 memory controller for a 32-bit data bus width.

CL

4h

To select a CAS latency of 4.

IBANK

3h

To select 8 internal DDR2 banks.

PAGESIZE

2h

To select 1024-word page size.

3.2.2Programming the SDRAM Refresh Control Register (SDRFC)

The SDRAM refresh control register (SDRFC) configures the DDR2 memory controller to meet the refresh requirements of the attached DDR2 device. SDRFC also allows the DDR2 memory controller to enter and exit self refresh. In this example, we assume that the DDR2 memory controller is not is in self-refresh mode.

The REFRESH_RATE field in SDRFC is defined as the rate at which the attached DDR2 device is refreshed in DDR2 cycles. The value of this field may be calculated using the following equation:

REFRESH_RATE = DDR_CLK frequency × memory refresh period

SPRUEK5A –October 2007

DSP DDR2 Memory Controller

33

Page 32 Page 34
Image 33
Page 32 Page 34
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable BytesAddress Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionSelf-Refresh Mode Reset ConsiderationsReset Sources DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function SelectionSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionOffset Acronym Register Description DDR2 Memory Controller RegistersDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp TckeBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register DmcctlAdditions/Modifications/Deletions Table A-1. Document Revision HistoryProducts Applications DSPRfid
Top Page Image Contents