Texas Instruments DM648 DSP, TMS320DM647 manual Connecting to a Single 16-Bit DDR2 Sdram Device

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Using the DDR2 Memory Controller

Figure 18. Connecting to a Single 16-Bit DDR2 SDRAM Device

DDR_CLK

DDR_CLK

DDR_CKE

DDR2 DDR_CS memory controller DDR_WE

DDR_RAS

DDR_CAS

DDR_DQM0

DDR_DQM1

DDR_DQS0

DDR_DQS0

DDR_DQS1

DDR_DQS1

DDR_BA[2:0]

DDR_A[13:0]

DDR_D[15:0]

DDR_ODT0

DDR_ODT1

DDR_VREF

DDR_DQGATE0(A)

DDR_DQGATE1(A)

DDR_DQGATE2(A)

DDR_DQGATE3(A)

VREF

CK

CK

CKE

CS DDR2 memory

WE x16−bit

RAS

CAS

LDM

UDM

LDQS

LDQS

UDQS

UDQS

BA[2:0]

A[12:0]

DQ[15:0]

ODT

VREF

AThese pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual.

SPRUEK5A –October 2007	DSP DDR2 Memory Controller	31
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsReset Considerations Self-Refresh ModeReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise Rese DDR2 Memory Controller Control Register DmcctlAdditions/Modifications/Deletions Table A-1. Document Revision HistoryDSP Products ApplicationsRfid