Texas Instruments DM648 DSP Module ID and Revision Register Midr, Bit Field Value Description

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DDR2 Memory Controller Registers

4.1Module ID and Revision Register (MIDR)

The Module ID and Revision register (MIDR) is shown in Figure 20 and described in Table 18.

Figure 20. Module ID and Revision Register (MIDR)

31	30	29		16
Reserved				MOD_ID
	R-0x0			R-0x0031
15		8	7	0
		MJ_REV		MN_REV
		R-0x03		R-0x0F
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

		Table 18. Module ID and Revision Register (MIDR) Field Descriptions
Bit	Field	Value Description
31-30	Reserved	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
29-16	MOD_ID	Module ID bits.
15-8	MJ_REV	Major revision.
7-0	MN_REV	Minor revision.

4.2DDR2 Memory Controller Status Register (DMCSTAT)

The DDR2 memory controller status register (DMCSTAT) is shown in Figure 21 and described in Table 19.

Figure 21. DDR2 Memory Controller Status Register (DMCSTAT)

31	30	29				16
Rsvd	Rsvd		Reserved
R-0x0 R-0x1			R-0x0
15			3	2	1	0
		Reserved		IFRDY	Reserved
		R-0x0		R-0x0		R-0x0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 19. DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions

Bit	Field	Value	Description
31	Reserved	0	Reserved. The value always should be written as 0. write of 1 results an error in functionality.
30	Reserved	1	Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
29-3	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
2	IFRDY		DDR2 memory controller interface logic ready bit. The interface logic controls the signals used to
			communicate with DDR2 SDRAM devices. This bit displays the status of the interface logic.
		0	Interface logic is not ready; either powered down, not ready, or not locked.
		1	Interface logic is powered up, locked, and ready for operation.
1-0	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SPRUEK5A –October 2007	DSP DDR2 Memory Controller	37
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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable BytesAddress Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Considerations Self-Refresh ModeReset Sources DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function SelectionSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionOffset Acronym Register Description DDR2 Memory Controller RegistersDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp TckeBurst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise Rese DDR2 Memory Controller Control Register DmcctlAdditions/Modifications/Deletions Table A-1. Document Revision HistoryDSP Products ApplicationsRfid