Texas Instruments DM648 DSP, TMS320DM647 manual Contents

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Contents

Preface			6
1	Introduction		9
	1.1	Purpose of the Peripheral	9
	1.2	Features	9
	1.3	Functional Block Diagram	9
	1.4	Industry Standard(s) Compliance Statement	10
2	Peripheral Architecture		11
	2.1	Clock Control	11
	2.2	Memory Map	11
	2.3	Signal Descriptions	11
	2.4	Protocol Description(s)	13
	2.5	Memory Width and Byte Alignment	18
	2.6	Address Mapping	19
	2.7	DDR2 Memory Controller Interface	22
	2.8	Refresh Scheduling	25
	2.9	Self-Refresh Mode	26
	2.10	Reset Considerations	26
	2.11	DDR2 SDRAM Memory Initialization	27
	2.12	Interrupt Support	28
	2.13	EDMA Event Support	28
	2.14	Emulation Considerations	28
3	Using the DDR2 Memory Controller		29
	3.1	Connecting the DDR2 Memory Controller to DDR2 SDRAM	29
	3.2	Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications	33
4	DDR2 Memory Controller Registers		36
	4.1	Module ID and Revision Register (MIDR)	37
	4.2	DDR2 Memory Controller Status Register (DMCSTAT)	37
	4.3	SDRAM Configuration Register (SDCFG)	38
	4.4	SDRAM Refresh Control Register (SDRFC)	40
	4.5	SDRAM Timing 1 Register (SDTIM1)	41
	4.6	SDRAM Timing 2 Register (SDTIM2)	43
	4.7	Burst Priority Register (BPRIO)	44
	4.8	DDR2 Memory Controller Control Register (DMCCTL)	45
Appendix A		Revision History	46

SPRUEK5A –October 2007

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Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal DescriptionsProtocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command FunctionCOL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas DdrweDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory RangesIbank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit DescriptionLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency LevelsSelf-Refresh Mode Reset ConsiderationsReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 ConfigurationEdma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register SdrfcSDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet ParameterOffset Acronym Register Description DDR2 Memory Controller RegistersBit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcTras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWRDDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt TsxnrBurst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register DmcctlAdditions/Modifications/Deletions Table A-1. Document Revision HistoryProducts Applications DSPRfid