Texas Instruments DM648 DSP Sdram Timing 1 Register SDTIM1, Trfc TRP Trcd TWR, Tras TRC Trrd

Page 41

www.ti.com

DDR2 Memory Controller Registers

4.5SDRAM Timing 1 Register (SDTIM1)

The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2 memory data sheet for information on the appropriate values to program each field. The bit fields in the SDTIM1 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked. The SDTIM1 is shown in Figure 24 and described in

Table 22.

Figure 24. SDRAM Timing 1 Register (SDTIM1)

31

 

 

25

24

22

21

19

18

 

16

 

T_RFC

 

 

T_RP

 

 

T_RCD

 

T_WR

 

 

R/W-0x3F

 

 

R/W-0x7

 

 

R/W-0x7

 

R/W-0x7

 

15

11

10

 

 

6

5

3

2

1

0

 

T_RAS

 

 

T_RC

 

 

T_RRD

Rsvd

T_WTR

 

R/W-0x1F

 

 

R/W-0x1F

 

 

R/W-0x7

R-0

R/W-0x3

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Bit Field

31-25 T_RFC

24-22 T_RP

21-19 T_RCD

18-16 T_WR

15-11 T_RAS

10-6 T_RC

5-3 T_RRD

2

Reserved

Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions

Value Description

These bits specify the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh or activate command, minus one. The value for these bits can be derived from the trfc AC timing parameter in the DDR2 memory data sheet. Calculate using this formula:

T_RFC = (trfc/DDR_CLK) - 1

These bits specify the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate command, minus 1. The value for these bits can be derived from the trp AC timing parameter in the DDR2 memory data sheet. Calculate using the formula:

T_RP = (trp/DDR_CLK) - 1

These bits specify the minimum number of DDR_CLK cycles from an activate command to a read or write command, minus 1. The value for these bits can be derived from the trcd AC timing parameter in the DDR2 memory data sheet. Calculate using the formula:

T_RCD = (trcd/DDR_CLK) - 1

These bits specify the minimum number of DDR_CLK cycles from the last write transfer to a precharge command, minus 1. The value for these bits can be derived from the twr AC timing parameter in the DDR2 memory data sheet. Calculate using the formula:

T_WR = (twr/DDR_CLK) - 1

The SDRAM initialization sequence will be started when the value of this field is changed from the previous value and the DDR2_ENABLE in SDCFG is equal to 1.

These bits specify the minimum number of DDR_CLK cycles from an activate command to a precharge command, minus 1. The value for these bits can be derived from the tras AC timing parameter in the DDR2 memory data sheet. Calculate using this formula:

T_RAS = (tras/DDR_CLK) - 1

T_RAS must be greater than or equal to T_RCD.

These bits specify the minimum number of DDR_CLK cycles from an activate command to an activate command, minus 1. The value for these bits can be derived from the trc AC timing parameter in the DDR2 memory data sheet. Calculate using this formula:

T_RC = (trc/DDR_CLK) - 1

These bits specify the minimum number of DDR_CLK cycles from an activate command to an activate command in a different bank, minus 1. The value for these bits can be derived from the trrd AC timing parameter in the DDR2 memory data sheet. Calculate using this formula:

T_RRD = (trrd/DDR_CLK) - 1

When connecting to an 8_bank DDR2 SDRAM, this field must be equal to:

T_RRD = ( (4*trrd + 2*tck) / (4*tck) ) - 1

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SPRUEK5A –October 2007

DSP DDR2 Memory Controller

41

Submit Documentation Feedback

 

 

Page 40 Page 42
Image 41
Page 40 Page 42
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal DescriptionsTruth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol DescriptionsRefresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COLDdrcs Ddrras Ddrcas Ddrwe Activation ActvDeactivation Dcab and Deac Dcab CommandDDR2 Read Command Read CommandMemory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable BytesAddress Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller InterfaceCommand Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block DiagramCommand Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level DescriptionReset Sources Self-Refresh ModeReset Considerations DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event SupportConnecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory ControllerConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function SelectionSdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 ConfigurationDmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name DescriptionOffset Acronym Register Description DDR2 Memory Controller RegistersDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value DescriptionSdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register SdcfgSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register SdrfcSdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions Rese DDR2 Memory Controller Control Register DmcctlAdditions/Modifications/Deletions Table A-1. Document Revision HistoryRfid Products ApplicationsDSP
Top Page Image Contents