Texas Instruments TMS320DM647, DM648 DSP Mode Register Set MRS and Emrs, Refresh Mode, Col, Bank

Page 14

www.ti.com

Peripheral Architecture

2.4.1Mode Register Set (MRS and EMRS)

DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc.

The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on DDR_BA[1:0] selects the mode register to be written and the data on DDR_A[12:0] is loaded into the register. Figure 3 shows the timing for an MRS and EMRS command.

The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller initialization sequence. See Section 2.11 for more information.

Figure 3. DDR2 MRS and EMRS Command

 

DDR_CLK

 

 

 

 

 

 

 

MRS/EMRS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_CKE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_CS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_RAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_CAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_A[13:0]

 

 

 

 

COL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR_BA[2:0]

 

 

 

 

 

BANK

 

 

 

 

2.4.2Refresh Mode

The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC). Page information is always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within the DDR2 memory controller. See Section 2.8 for more details on REFR command scheduling.

14

DSP DDR2 Memory Controller

SPRUEK5A –October 2007

Page 13 Page 15
Image 14
Page 13 Page 15
Contents Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Related Documentation From Texas Instruments Trademarks Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control DDR2 Memory Controller Signal Descriptions Pin DescriptionCommand Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol DescriptionsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COLActivation Actv Ddrcs Ddrras Ddrcas DdrweDcab Command Deactivation Dcab and DeacRead Command DDR2 Read CommandAddressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable BytesBit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping IbankLogical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo DescriptionDDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced ConceptCommand Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level DescriptionReset Sources Self-Refresh ModeReset Considerations DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory InitializationInterrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event SupportUsing the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 SdramConnecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function SelectionConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name DescriptionDDR2 Memory Controller Registers Offset Acronym Register DescriptionModule ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value DescriptionSdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field DescriptionsSdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field DescriptionsTrfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC TrrdDDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp TckePrioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl ReseTable A-1. Document Revision History Additions/Modifications/DeletionsRfid Products ApplicationsDSP
Top Page Image Contents