Texas Instruments MSP-FET430 manual Using an Existing IAR V1.x/V2.x Project

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Development Flow

Note: How to add assembler source files to your project

The default file type presented in the Add Files window is “C/C++ Files”. In order to view assembler files (.s43), select “Assembler Files” in the “Files of type” drop-down menu.

8)Configure the project options (PROJECT->OPTIONS). For each of the listed subcategories (GENERAL OPTIONS, C/C++ COMPILER, ASSEMBLER, LINKER, DEBUGGER), accept the default Factory Settings with the following exceptions:

Specify the target device (GENERAL OPTIONS->TARGET->DEVICE)

Enable an assembler project or a C/assembler project (GENERAL OPTIONS ->TARGET->ASSEMBLER ONLY PROJECT)

Enable the generation of an executable output file (GENERAL OPTIONS -

>OUTPUT->OUTPUT FILE->EXECUTABLE)

To debug on the FET (i.e., the MSP430), select DEBUGGER ->SETUP-

>DRIVER-> FET DEBUGGER

Specify the active port used to interface to the FET (FET DEBUGGER - >SETUP->CONNECTION)

8)Build the project (PROJECT->REBUILD ALL).

9)Debug the application using C-SPY (PROJECT->DEBUG). This will start C- SPY, and C-SPY will get control of the target, erase the target memory, program the target memory with the application, and reset the target.

Refer to FAQ, Debugging #1) if C-SPY is unable to communicate with the device.

10)Use DEBUG->GO to start the application.

11)Use DEBUG->STOP DEBUGGING to stop the application, to exit C-SPY, and to return to the Workbench.

12)Use FILE->EXIT to exit the Workbench.

2.2.3Using an Existing IAR V1.x/V2.x Project

It is possible to use an existing project from an IAR V1.x/V2.x system with the new IAR V3.x system; refer to the IAR document Step by step migration for EW430 x.xx. This document can be located in: <Installation Root>\Embedded Workbench x.x\430\doc\migration.htm

2.2.4Stack Management within the .xcl Files

The .xcl files are input to the linker, and contain statements that control the allocation of device memory (RAM, Flash). Refer to the IAR XLINK documentation for a complete description of these files. The .xcl files provided with the FET (<Installation Root>\Embedded Workbench x.x\430\config\lnk430xxxx.xcl) define a relocatable segment (RSEG) called CSTACK. CSTACK is used to define the region of RAM that is used for the

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Contents Users Guide 2004Important Notice Page July How to Use This Manual Read This FirstAbout This Manual Information About Cautions and Warnings Related Documentation From Texas InstrumentsIf You Need Assistance FCC WarningPage Contents Frequently Asked Questions Figures TablesPage Get Started Now TopicKit Contents, MSP-FET430X110 Kit Contents, MSP-FET430UIF Software InstallationHardware Installation, MSP-FET430X110 Hardware Installation, USB-IF, MSP-FET430UIF Flashing the LEDGet Started Now Important MSP430 Documents on the CD-ROM and WEB Development Flow Using Kickstart OverviewProject Settings OUTPUT-OUTPUT FILE-EXECUTABLEFactory Settings Creating a Project from Scratch Using an Existing IAR V1.x/V2.x Project Stack Management within the .xcl FilesHow to Generate Texas Instrument .TXT and other format Files Overview of Example ProgramsDevelopment Flow Using C-SPY Using BreakpointsBreakpoint Types Using Single Step Using Watch Windows Page Design Considerations for In-Circuit Programming Bootstrap Loader External PowerDesign Considerations for In-Circuit Programming Device Signals PRGS430Design Considerations for In-Circuit Programming Signal connections for MSP-FET430X110 Design Considerations for In-Circuit Programming Jtag Signal Connections Frequently Asked Questions Hardware Program Development Assembler, C-Compiler, Linker Should Done or Not Return Omit Debugging C-SPY OPTIONS-FET DEBUGGER-CONNECTIONSFrequently Asked Questions Figure A-1. Modification to FET Interface module Frequently Asked Questions Frequently Asked Questions Frequently Asked Questions Frequently Asked Questions Frequently Asked Questions Figure B-1. MSP-FET430X110, Schematic HardwareFigure B-1. MSP-FET430X110, Schematic Figure B-2. MSP-FET430X110, PCB Pictorials Figure B-3. MSP-FET430IF FET Interface module, Schematic Figure B-4. MSP-FET430IF FET Interface module, PCB Pictorial Figure B-5. MSP-TS430DW28 Target Socket module, Schematic LED connected to P1.0 Hardware Jumper J7 Jumper J6Open to measure current Hardware Jumper J6 Open to disconnect LED History of changes to MSP-TS430PM64 Target Socket module Figure B-11. MSP-TSPN80 Target Socket module, Schematic Figure B-12. MSP-TSPN80 Target Socket module, PCB Pictorials Figure B-13. MSP-TSPZ100 Target Socket module, Schematic Jumper J6 Figure B-15. MSP-FET430UIF USB Interface schematics Hardware Hardware Hardware Hardware Page FET Specific Menus Emulator EMULATOR-POWER on Reset EMULATOR-GIE on/off EMULATOR-FORCE Single SteppingPin MSP430F44x and MSP430F43x Device Emulation Table D-1. F4xx/80-pin Signal Mapping P1.5/TACLK/ACLK P1.4/TBCLK/SMCLK P1.3/TBOUTH/SVSOUT Page TI to IAR 2.x/3.x Assembler Migration Segment Control Translating Asm430 Assembler Directives to A430 DirectivesIntroduction Character stringsSection Control Directives Description Asm430 Directive TI A430 Directive IARConstant Initialization Directives Listing Control DirectivesConditional-Assembly Directives File Reference DirectivesSymbol Control Directives ReptcMacro Directives Miscellaneous DirectivesPreprocessor Directives Additional A430 Directives IAR Asm430 directive A430 directiveLstpag + #if, #else, #elif Page MSP-FET430UIF Installation Guide Hardware Installation Figure F-1. WinXP Hardware RecognitionFigure F-3. WinXP Driver Location Selection Folder Figure F-4. WinXP Driver Installation Figure F-5. Device Manager