Cypress FX2LP, AN6077 manual Setupdat

Page 13
// Handled by user code

AN6077

}

BOOL TD_Suspend( void )

{// Called before the device goes into suspend mode return( TRUE );

}

BOOL TD_Resume( void )

{ // Called after the device resumes return( TRUE );

}

//-----------------------------------------------------------------------------

//Device Request hooks

//The following hooks are called by the end point 0 device request parser. //-----------------------------------------------------------------------------

BOOL DR_GetDescriptor( void )

{

return( TRUE );

}

BOOL DR_SetConfiguration( void )

{// Called when a Set Configuration command is received if( EZUSB_HIGHSPEED( ) )

{// FX2LP in high speed mode

SYNCDELAY;//

EP6AUTOINLENH = 0x02; // set core AUTO commit len = 512 bytes

SYNCDELAY;// EP6AUTOINLENL = 0x00;

SYNCDELAY;//

enum_pkt_size = 512; // max. pkt. size = 512 bytes

}

else

{// FX2LP in full speed mode

SYNCDELAY;//

EP6AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes

SYNCDELAY;// EP6AUTOINLENL = 0x40;

SYNCDELAY;

= 64;

//

enum_pkt_size

// max. pkt. size = 64 bytes

}

 

 

Configuration =

SETUPDAT[

2 ];

return( TRUE );

//

Handled by user code

}

BOOL DR_GetConfiguration( void )

{// Called when a Get Configuration command is received EP0BUF[ 0 ] = Configuration;

EP0BCH = 0;

EP0BCL = 1; return(TRUE);

}

BOOL DR_SetInterface( void )

{// Called when a Set Interface command is received AlternateSetting = SETUPDAT[ 2 ];

return( TRUE );

//

Handled by user code

 

}

 

 

 

BOOL DR_GetInterface( void )

 

 

February 19, 2008

 

Document No. 001-15342 Rev. **

13

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Image 13
Contents Introduction Application Note AbstractSlave Fifo Pin Descriptions Gpif Master Pin DescriptionsCreating Gpif Waveforms Fifowr Firmware Architecture Firmware Programming MasterPsuedocode for Master Psuedocode for Master OUTExpanded Master OUT Code Expanded Master in Code Syncdelay Gpiftrig = Gpiftrigwr GPIFEP2Firmware for the Slave SyncdelaySummary Gpiftrig = Gpiftrigrd GPIFEP6Code Listing for Master Side EP4 and EP8 are not used in this implementation Gpiftrig Trigger Fifo write transactions, using SFR Syncdelay Gpiftrig = Gpiftrigrd GPIFEP6 Setupdat Ezusbirqclear = TrueUsbirq Clear Ures IRQ + Feedback Code Listing for the Slave Side AUTOOUT=0, WORDWIDE=0 Syncdelay AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 AUTOOUT=1, WORDWIDE=0EP0BCH EP0BCL Clear Ures IRQ + Feedback + Feedback