Cypress FX2LP, AN6077 manual Psuedocode for Master OUT, Expanded Master OUT Code

Page 5

AN6077

The firmware uses the AUTO mode for both IN and OUT transfers. This means that the maximum size (512 bytes) packets are committed automatically from the peripheral domain to the USB domain for OUT transfers. For IN trans- fers, they are committed from USB to the peripheral domain.

The 8051 is not involved in committing packets. Short pack- ets are handled by the master strobing the PKTEND of the slave. In this implementation, the PKTEND of the slave is tied to CTL2 of the master. So the GPIFIDLECTL register is writ- ten to strobe PKTEND.

Psuedocode for Master OUT

if GPIF is IDLE

if there is a packet in EP2 OUT if the peripheral is not FULL

trigger the GPIF Write Transaction // handle short packet

if the transaction count < 512 if GPIF is IDLE

strobe PKTEND else

//do nothing; wait for GPIF to be done

else

//do nothing; packet is not short packet

else

//do nothing; peripheral is FULL

else

//do nothing; no data is available to transfer else

//do nothing; GPIF is not IDLE

Psuedocode for Master IN

if the GPIF is IDLE

if the peripheral is not empty if EP6 IN is not full

trigger the GPIF Read transaction if packet is short packet

commit the packet by writing INPKTEND else

//do nothing; packet is not short else

//do nothing; EP6 IN is full else

//do nothing; the peripheral does not have data to transfer else

//do nothing; GPIF is busy

Expanded Master OUT Code

if( GPIFTRIG & 0x80 )

{

//DONE=1, when GPIF is "idle"

//check if there is a packet in the peripheral domain (EP2OUT) if( EP24FIFOFLGS & 0x02 )

{

//EF=1 when buffer "empty", for example, no more data to transfer

}

else

{

//EF=0, when slave fifo is "not empty"

//the cpu passed the packet to the peripheral domain (AUTO OUT)

//check if peripheral "not full"

if( GPIFREADYSTAT & 0x02 )

{

//RDY1=1, when peripheral is "not" FULL (tied to peripheral "full" flag)

//drive FIFOADDR lines

OEA = 0xC0;

February 19, 2008

Document No. 001-15342 Rev. **

5

[+] Feedback

Image 5
Contents Introduction Application Note AbstractCreating Gpif Waveforms Gpif Master Pin DescriptionsSlave Fifo Pin Descriptions Fifowr Firmware Architecture Firmware Programming MasterExpanded Master OUT Code Psuedocode for Master OUTPsuedocode for Master Expanded Master in Code Syncdelay Gpiftrig = Gpiftrigwr GPIFEP2Firmware for the Slave SyncdelaySummary Gpiftrig = Gpiftrigrd GPIFEP6Code Listing for Master Side EP4 and EP8 are not used in this implementation Gpiftrig Trigger Fifo write transactions, using SFR Syncdelay Gpiftrig = Gpiftrigrd GPIFEP6 Setupdat Usbirq = TrueEzusbirqclear Clear Ures IRQ + Feedback Code Listing for the Slave Side AUTOOUT=0, WORDWIDE=0 Syncdelay AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 AUTOOUT=1, WORDWIDE=0EP0BCH EP0BCL Clear Ures IRQ + Feedback + Feedback