Cypress FX2LP, AN6077 manual Fifowr

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AN6077

Figure 2 shows the GPIF Designer view of the FIFO Read waveform.

FIFOWR

When creating the FIFOWR waveform the following timing parameters must be met.

tWRpwl - SLWR Pulse Width LOW = 50 ns (minimum)

tWRpwh - SLWR Pulse Width HIGH = 50 ns (minimum)

tSFD - SLWR to FIFO DATA Setup Time= 10 ns (mini- mum)

tFDH - FIFO DATA to SLWR Hold Time = 10 ns (minimum)

This results in the following sequence:

s0 Sample the full flag of the peripheral. If the peripheral is ‘not full’, proceed to s1, otherwise proceed to s6 to trigger an interrupt and abort the GPIF waveform.

s1 Assert the SLWR strobe and drive the data bus and wait for three cycles to meet the tWRpwl parameter.

s2 Deassert the SLWR and increment the FIFO pointer.

s3 Branch to IDLE.

Figure 3 shows the GPIF Designer view of the FIFO Write waveform. Figure 4 and Figure 5 show the view of the GPIF waveforms in the gpif.c file. This is the same as is seen in the GPIF Tool utility.

tXFD - SLWR to FLAGS Output Propagation Delay = 70 ns (maximum)

Figure 2. FIFO Read Waveform in GPIF Designer

Figure 3. FIFO Write Waveform in GPIF Designer

February 19, 2008

Document No. 001-15342 Rev. **

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Contents Introduction Application Note AbstractGpif Master Pin Descriptions Slave Fifo Pin DescriptionsCreating Gpif Waveforms Fifowr Firmware Architecture Firmware Programming MasterPsuedocode for Master OUT Psuedocode for MasterExpanded Master OUT Code Expanded Master in Code Syncdelay Gpiftrig = Gpiftrigwr GPIFEP2Gpiftrig = Gpiftrigrd GPIFEP6 SyncdelayFirmware for the Slave SummaryCode Listing for Master Side EP4 and EP8 are not used in this implementation Gpiftrig Trigger Fifo write transactions, using SFR Syncdelay Gpiftrig = Gpiftrigrd GPIFEP6 Setupdat = True EzusbirqclearUsbirq Clear Ures IRQ + Feedback Code Listing for the Slave Side AUTOOUT=0, WORDWIDE=0 Syncdelay AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 AUTOOUT=1, WORDWIDE=0EP0BCH EP0BCL Clear Ures IRQ + Feedback + Feedback