Cypress FX2LP, AN6077 manual Clear Ures IRQ

Page 21

AN6077

USBIRQ = bmSOF;

// Clear SOF IRQ

}

void ISR_Ures( void ) interrupt 0

{

if ( EZUSB_HIGHSPEED( ) )

{

pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr;

}

else

{

pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr;

}

 

EZUSB_IRQ_CLEAR( );

// Clear URES IRQ

USBIRQ = bmURES;

}

void ISR_Susp( void ) interrupt 0

{

Sleep = TRUE; EZUSB_IRQ_CLEAR( ); USBIRQ = bmSUSP;

}

void ISR_Highspeed( void ) interrupt 0

{

if ( EZUSB_HIGHSPEED( ) )

{

pConfigDscr = pHighSpeedConfigDscr; pOtherConfigDscr = pFullSpeedConfigDscr;

}

else

{

pConfigDscr = pFullSpeedConfigDscr; pOtherConfigDscr = pHighSpeedConfigDscr;

}

EZUSB_IRQ_CLEAR( ); USBIRQ = bmHSGRANT;

}

void ISR_Ep0ack( void ) interrupt 0

{

}

void ISR_Stub( void ) interrupt 0

{

}

void ISR_Ep0in( void ) interrupt 0

{

}

void ISR_Ep0out( void ) interrupt 0

{

}

void ISR_Ep1in( void ) interrupt 0

{

}

void ISR_Ep1out( void ) interrupt 0

{

}

void ISR_Ep2inout( void ) interrupt 0

{

February 19, 2008

Document No. 001-15342 Rev. **

21

Image 21
Contents Introduction Application Note AbstractGpif Master Pin Descriptions Slave Fifo Pin DescriptionsCreating Gpif Waveforms Fifowr Firmware Architecture Firmware Programming MasterPsuedocode for Master OUT Psuedocode for MasterExpanded Master OUT Code Expanded Master in Code Syncdelay Gpiftrig = Gpiftrigwr GPIFEP2Firmware for the Slave SyncdelaySummary Gpiftrig = Gpiftrigrd GPIFEP6Code Listing for Master Side EP4 and EP8 are not used in this implementation Gpiftrig Trigger Fifo write transactions, using SFR Syncdelay Gpiftrig = Gpiftrigrd GPIFEP6 Setupdat = True EzusbirqclearUsbirq Clear Ures IRQ + Feedback Code Listing for the Slave Side AUTOOUT=0, WORDWIDE=0 Syncdelay AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 AUTOOUT=1, WORDWIDE=0EP0BCH EP0BCL Clear Ures IRQ + Feedback + Feedback