Cypress FX2LP, AN6077 manual Code Listing for the Slave Side

Page 17

AN6077

}

void ISR_Ep8fflag( void ) interrupt 0

{

}

void ISR_GpifComplete( void ) interrupt 0

{

}

void ISR_GpifWaveform( void ) interrupt 0

{// FIFORd WF detected peripheral prematurely empty (less than max. pkt. size)

GPIFABORT = 0xFF;

// abort to handle shortpkt

INPKTEND = 0x06;

 

SYNCDELAY;

 

EXIF &= ~0x40;

// automatically enabled at POR

INT4CLR = 0xFF;

SYNCDELAY;

 

}

 

Code Listing for the Slave Side

#pragma NOIV

// Do not generate interrupt vectors

#include "fx2.h"

 

#include "fx2regs.h"

// SYNCDELAY macro

#include "fx2sdly.h"

extern BOOL GotSUD;

// Received setup data flag

extern BOOL Sleep;

 

extern BOOL Rwuen;

 

extern BOOL Selfpwr;

 

BYTE Configuration;

// Current configuration

BYTE AlternateSetting;

// Alternate settings

//-----------------------------------------------------------------------------

//Task Dispatcher hooks

//The following hooks are called by the task dispatcher.

//-----------------------------------------------------------------------------

TD_Init( void )

void

{ //

Called once at startup

CPUCS = 0x10;

// CLKSPD[1:0]=10, for 48 MHz operation

SYNCDELAY;

 

REVCTL=0x02;

 

IFCONFIG = 0xCB;

, FIFOs executes on internal clk source

//

IFCLKSRC=1

//

x MHz=1

, 48 MHz internal clk rate

//

IFCLKOE=0

, Don't drive IFCLK pin signal at 48 MHz

//

IFCLKPOL=0

, Don't invert IFCLK pin signal from internal clk

//

ASYNC=1

, master samples asynchronous

//

GSTATE=0

, Don't drive GPIF states out on PORTE[2:0], debug WF

//IFCFG[1:0]=11, FX2 in slave FIFO mode

//Registers which require a synchronization delay, see section 15.14

// FIFORESET

FIFOPINPOLAR

 

// INPKTEND

OUTPKTEND

 

// EPxBCH:L

REVCTL

 

// GPIFTCB3

GPIFTCB2

 

// GPIFTCB1

GPIFTCB0

 

// EPxFIFOPFH:L

EPxAUTOINLENH:L

 

// EPxFIFOCFG

EPxGPIFFLGSEL

 

February 19, 2008

Document No. 001-15342 Rev. **

17

Image 17
Contents Introduction Application Note AbstractCreating Gpif Waveforms Gpif Master Pin DescriptionsSlave Fifo Pin Descriptions Fifowr Firmware Architecture Firmware Programming MasterExpanded Master OUT Code Psuedocode for Master OUTPsuedocode for Master Expanded Master in Code Syncdelay Gpiftrig = Gpiftrigwr GPIFEP2Firmware for the Slave SyncdelaySummary Gpiftrig = Gpiftrigrd GPIFEP6Code Listing for Master Side EP4 and EP8 are not used in this implementation Gpiftrig Trigger Fifo write transactions, using SFR Syncdelay Gpiftrig = Gpiftrigrd GPIFEP6 Setupdat Usbirq = TrueEzusbirqclear Clear Ures IRQ + Feedback Code Listing for the Slave Side AUTOOUT=0, WORDWIDE=0 Syncdelay AUTOIN=1, ZEROLENIN=1, WORDWIDE=0 AUTOOUT=1, WORDWIDE=0EP0BCH EP0BCL Clear Ures IRQ + Feedback + Feedback