Code Listing for Master Side

AN6077

#pragma NOIV	// Do not generate interrupt vectors
#include "fx2.h"
#include "fx2regs.h"	// SYNCDELAY macro
#include "fx2sdly.h"	// SYNCDELAY macro
extern BOOL GotSUD;	// Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration;	// Current configuration
BYTE AlternateSetting;	// Alternate settings

//proto's from "gpif.c" void GpifInit( void );

//512 for high speed, 64 for full speed static WORD enum_pkt_size = 0x0000;

//when set firmware running in TD_Poll( ); handles data transfers BOOL td_poll_handles_transfers = 1;

//when set cpu is out of the data path

BOOL endp_auto_mode_enabled = 1;

//-----------------------------------------------------------------------------

// Task Dispatcher hooks

//	The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------	TD_Init( void )
void	TD_Init( void )
{ //	Called once at startup
CPUCS = 0x10;		// CLKSPD[1:0]=10, for 48 MHz operation
		// CLKOE=0, don't drive CLKOUT
GpifInit( );		// init GPIF engine via GPIFTool output file
//	Registers which require a synchronization delay, see section 15.14
//	FIFORESET	FIFOPINPOLAR
//	INPKTEND	OUTPKTEND
//	EPxBCH:L	REVCTL
//	GPIFTCB3	GPIFTCB2
//	GPIFTCB1	GPIFTCB0
//	EPxFIFOPFH:L	EPxAUTOINLENH:L
//	EPxFIFOCFG	EPxGPIFFLGSEL
//	PINFLAGSxx	EPxFIFOIRQ
//	EPxFIFOIE	GPIFIRQ
//	GPIFIE	GPIFADRH:L
//	UDMACRCH:L	EPxGPIFTRIG
//	GPIFTRIG
SYNCDELAY;		// see TRM section 15.14
REVCTL = 0x02;		// REVCTL.1=1;
SYNCDELAY;		// BUF[1:0]=00 for 4x buffering
EP2CFG = 0xA0;		// BUF[1:0]=00 for 4x buffering

//EP6 512 BULK IN 4x SYNCDELAY;

EP6CFG = 0xE0;	// BUF[1:0]=00 for 4x buffering
February 19, 2008	Document No. 001-15342 Rev. **	8

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