Cypress AN6077, FX2LP manual + Feedback

Page 22

AN6077

}

void ISR_Ep4inout( void ) interrupt 0

{

}

void ISR_Ep6inout( void ) interrupt 0

{

}

void ISR_Ep8inout( void ) interrupt 0

{

}

void ISR_Ibn( void ) interrupt 0

{

}

void ISR_Ep0pingnak( void ) interrupt 0

{

}

void ISR_Ep1pingnak( void ) interrupt 0

{

}

void ISR_Ep2pingnak( void ) interrupt 0

{

}

void ISR_Ep4pingnak( void ) interrupt 0

{

}

void ISR_Ep6pingnak( void ) interrupt 0

{

}

void ISR_Ep8pingnak( void ) interrupt 0

{

}

void ISR_Errorlimit( void ) interrupt 0

{

}

void ISR_Ep2piderror( void ) interrupt 0

{

}

void ISR_Ep4piderror( void ) interrupt 0

{

}

void ISR_Ep6piderror( void ) interrupt 0

{

}

void ISR_Ep8piderror( void ) interrupt 0

{

}

void ISR_Ep2pflag( void ) interrupt 0

{

}

void ISR_Ep4pflag( void ) interrupt 0

{

}

void ISR_Ep6pflag( void ) interrupt 0

{

}

void ISR_Ep8pflag( void ) interrupt 0

{

}

void ISR_Ep2eflag( void ) interrupt 0

{

}

void ISR_Ep4eflag( void ) interrupt 0

{

February 19, 2008

Document No. 001-15342 Rev. **

22

Image 22
Contents Application Note Abstract IntroductionSlave Fifo Pin Descriptions Gpif Master Pin DescriptionsCreating Gpif Waveforms Fifowr Firmware Programming Master Firmware ArchitecturePsuedocode for Master Psuedocode for Master OUTExpanded Master OUT Code Syncdelay Gpiftrig = Gpiftrigwr GPIFEP2 Expanded Master in CodeSummary SyncdelayFirmware for the Slave Gpiftrig = Gpiftrigrd GPIFEP6Code Listing for Master Side EP4 and EP8 are not used in this implementation Gpiftrig Trigger Fifo write transactions, using SFR Syncdelay Gpiftrig = Gpiftrigrd GPIFEP6 Setupdat Ezusbirqclear = TrueUsbirq Clear Ures IRQ + Feedback Code Listing for the Slave Side AUTOOUT=0, WORDWIDE=0 Syncdelay AUTOOUT=1, WORDWIDE=0 AUTOIN=1, ZEROLENIN=1, WORDWIDE=0EP0BCH EP0BCL Clear Ures IRQ + Feedback + Feedback