Cypress CY7C1170V18 TAP Controller Block Diagram, TAP Electrical Characteristics, Gnd ≤ Vi ≤ Vdd

Page 15

CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

TAP Controller Block Diagram

Figure 3. Tap Controller Block Diagram

TDI

					0
			Bypass Register
Selection			2	1	0	Selection	TDO
Circuitry	Instruction Register					Circuitry
	Instruction Register
31	30 29 . .		2	1	0
	Identification Register
106	. .	. .	2	1	0
	Boundary Scan Register

TCK TMS

TAP Controller

TAP Electrical Characteristics

The Tap Electrical Characteristics table over the operating range follows.[10, 11, 12]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65 VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35 VDD	V
IX	Input and Output Load Current	GND ≤ VI ≤ VDD	−5	5	μA

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

11.Overshoot: VIH(AC) < VDDQ + 0.35V (pulse width less than tCYC/2), undershoot: VIL(AC) > −0.3V (pulse width less than tCYC/2).

12.All voltage refer to ground.

Document Number: 001-06620 Rev. *D

Page 15 of 27

[+] Feedback

Image 15

Contents Description 400 MHz 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional DescriptionLogic Block Diagram CY7C1177V18 Logic Block Diagram CY7C1166V18Logic Block Diagram CY7C1170V18 Logic Block Diagram CY7C1168V18TMS Pin ConfigurationsCY7C1166V18 2M x CY7C1177V18 2M xTMS TDI CY7C1168V18 1M xCY7C1170V18 512K x BWSNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Truth TableSRAM#1 SRAM#2 MasterDuring the Data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1170V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsAC Input Requirements Electrical CharacteristicMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Parameter Min MaxHigh LOWSwitching Waveform Read/Write/Deselect SequenceNOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR