Cypress CY7C1170V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Page 7

 

 

 

 

 

 

CY7C1166V18, CY7C1177V18

 

 

 

 

 

 

CY7C1168V18, CY7C1170V18

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

Pin Name

IO

 

 

Pin Description

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

 

 

 

 

bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

 

 

 

 

connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which

 

 

 

 

enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-

 

 

 

 

nected.

 

 

 

 

 

 

 

 

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

 

DOFF

 

 

 

 

timings in the DLL turned off operation is different from those listed in this data sheet. For normal

 

 

 

 

operation, this pin can be connected to a pull up through a 10KΩ or less pull up resistor. The device

 

 

 

 

behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a

 

 

 

 

frequency of up to 167 MHz with DDR-I timing.

 

 

 

 

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

 

 

 

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/36M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/72M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and

 

 

 

Reference

AC measurement points.

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 001-06620 Rev. *D

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Contents Description 400 MHz 375 MHz 333 MHz 300 MHz Unit FeaturesConfigurations Selection Guide Functional DescriptionLogic Block Diagram CY7C1177V18 Logic Block Diagram CY7C1166V18Logic Block Diagram CY7C1170V18 Logic Block Diagram CY7C1168V18TMS Pin ConfigurationsCY7C1166V18 2M x CY7C1177V18 2M xTMS TDI CY7C1168V18 1M xCY7C1170V18 512K x BWSNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Truth TableSRAM#1 SRAM#2 MasterDuring the Data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredDevice. D80 and D3518 remains unaltered Write cycle descriptions of CY7C1170V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramParameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics TAP ControllerTAP Timing and Test Condition TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsAC Input Requirements Electrical CharacteristicMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Parameter Min MaxHigh LOWRead/Write/Deselect Sequence Switching WaveformNOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramVKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History NXR
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