Cypress CY7C1168V18, CY7C1166V18, CY7C1177V18, CY7C1170V18 manual Ordering Information

Page 24

CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
400	CY7C1166V18-400BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1177V18-400BZC

	CY7C1168V18-400BZC

	CY7C1170V18-400BZC

	CY7C1166V18-400BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1177V18-400BZXC

	CY7C1168V18-400BZXC

	CY7C1170V18-400BZXC

	CY7C1166V18-400BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1177V18-400BZI

	CY7C1168V18-400BZI

	CY7C1170V18-400BZI

	CY7C1166V18-400BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1177V18-400BZXI

	CY7C1168V18-400BZXI

	CY7C1170V18-400BZXI

375	CY7C1166V18-375BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1177V18-375BZC

	CY7C1168V18-375BZC

	CY7C1170V18-375BZC

	CY7C1166V18-375BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1177V18-375BZXC

	CY7C1168V18-375BZXC

	CY7C1170V18-375BZXC

	CY7C1166V18-375BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1177V18-375BZI

	CY7C1168V18-375BZI

	CY7C1170V18-375BZI

	CY7C1166V18-375BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1177V18-375BZXI

	CY7C1168V18-375BZXI

	CY7C1170V18-375BZXI

Document Number: 001-06620 Rev. *D

Page 24 of 27

[+] Feedback

Image 24

Contents Features ConfigurationsSelection Guide Functional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1166V18 Logic Block Diagram CY7C1177V18Logic Block Diagram CY7C1168V18 Logic Block Diagram CY7C1170V18Pin Configurations CY7C1166V18 2M xCY7C1177V18 2M x TMSCY7C1168V18 1M x CY7C1170V18 512K xBWS TMS TDIPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Truth Table SRAM#1 SRAM#2Master OperationWrite Cycle Descriptions CommentsRemains unaltered During the Data portion of a write sequenceWrite cycle descriptions of CY7C1170V18 follows DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristic Maximum RatingsOperating Range AC Input RequirementsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max HighLOW DLL TimingSwitching Waveform Read/Write/Deselect SequenceNOP Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP