Cypress CY7C1168V18, CY7C1166V18, CY7C1177V18, CY7C1170V18 manual Functional Overview

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CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18

Functional Overview

The CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface.

Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input and output timing are referenced to the rising edge of the Input clocks (K/K).

All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the input clocks (K and K) also.

All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K/K).

CY7C1168V18 is described in the following sections. The same basic descriptions apply to CY7C1166V18, CY7C1177V18, and CY7C1170V18.

Read Operations

The CY7C1168V18 is organized internally as a single array of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K the next 18-bit data word from the address location generated by the burst counter is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K/K). In order to maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K).

When read access is deselected, the CY7C1168V18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the negative Input clock (K). This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise the data presented to D[17:0] is latched and stored into the 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data is then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K).

When write access is deselected, the device ignores all inputs after the pending write operations are completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1168V18. A Write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write enables the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a Byte Write operation.

Double Data Rate Operation

The CY7C1168V18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1168V18 requires two No Operation (NOP) cycle when transitioning from a read to a write cycle. At higher frequencies, some applications may require a third NOP cycle to avoid contention.

If a read occurs after a write cycle, then the address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a Posted Write.

If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR-II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II+. CQ is referenced with respect to K and CQ is refer- enced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics” on page 22.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR-II+ device along with data output. This signal is also edge-aligned with the

Document Number: 001-06620 Rev. *D

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Contents Features ConfigurationsSelection Guide Functional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1166V18 Logic Block Diagram CY7C1177V18Logic Block Diagram CY7C1168V18 Logic Block Diagram CY7C1170V18Pin Configurations CY7C1166V18 2M xCY7C1177V18 2M x TMSCY7C1168V18 1M x CY7C1170V18 512K xBWS TMS TDIPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Truth Table SRAM#1 SRAM#2Master OperationWrite Cycle Descriptions CommentsRemains unaltered During the Data portion of a write sequenceWrite cycle descriptions of CY7C1170V18 follows DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristic Maximum RatingsOperating Range AC Input RequirementsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max HighLOW DLL TimingNOP Switching WaveformRead/Write/Deselect Sequence Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP
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