Cypress CY7C1177V18, CY7C1168V18, CY7C1166V18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

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CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

Package Diagram

Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

15.00±0.10

TOP VIEW

PIN 1 CORNER

15.00±0.10

BOTTOM VIEW

							PIN 1 CORNER
					Ø0.05 M C
						Ø0.25 M C A B
					Ø0.50		-0.06	(165X)
							+0.14
11	10	9	8	7	6	5	4	3	2	1
										A
										B
1.00										C
1.00										D
										D
										E
										F
14.00										G
14.00										H
										J
										K
7.00										L
7.00										M
										M

1.00

5.00

10.00

0.25 C

	B
0.53±0.05
0.36	C
0.36

13.00±0.10

		1.40MAX.

				0.15C

SEATING PLANE

0.35±0.06

B 13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

Document Number: 001-06620 Rev. *D

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Contents Selection Guide Functional Description FeaturesConfigurations Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1166V18 Logic Block Diagram CY7C1177V18Logic Block Diagram CY7C1168V18 Logic Block Diagram CY7C1170V18CY7C1177V18 2M x Pin ConfigurationsCY7C1166V18 2M x TMSBWS CY7C1168V18 1M xCY7C1170V18 512K x TMS TDISynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Master Truth TableSRAM#1 SRAM#2 OperationRemains unaltered Write Cycle DescriptionsComments During the Data portion of a write sequenceInto the device. D359 remains unaltered Write cycle descriptions of CY7C1170V18 followsDevice Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsOperating Range Electrical CharacteristicMaximum Ratings AC Input RequirementsAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Parameter Min MaxHigh DLL TimingNOP Switching WaveformRead/Write/Deselect Sequence Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN/KKVTMP