Cypress CY7C1168V18, CY7C1166V18 manual Maximum Ratings, Operating Range, Electrical Characteristic

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CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with Power Applied. –55°C to + 125°C

Supply Voltage on VDD Relative to GND

–0.5V to + 2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to + VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage[11]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

20 mA

Static Discharge Voltage (MIL-STD-883, M 3015)....

>2001V

Latch up Current

>200 mA

Operating Range

 

Ambient

VDD[15]

VDDQ[15]

Range

Temperature

Commercial

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

VDD

Industrial

–40°C to +85°C

 

Electrical Characteristic

The DC Electrical Characteristics over the operating range follows.[12]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 16

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 17

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = –0.1 mA, Nominal Impedance

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

–0.15

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

–2

 

2

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

–2

 

2

μA

VREF

Input Reference Voltage[18]

Typical Value = 0.75V

 

0.68

0.75

0.95

V

IDD [19]

VDD Operating Supply

VDD = Max, IOUT = 0 mA,

300 MHz

 

 

850

mA

 

 

f = fmax = 1/tCYC

 

 

 

 

 

 

 

333 MHz

 

 

920

mA

 

 

 

375 MHz

 

 

1020

mA

 

 

 

 

 

 

 

 

 

 

 

400 MHz

 

 

1080

mA

 

 

 

 

 

 

 

 

ISB1

Automatic Power Down Current

Max VDD,

300 MHz

 

 

250

mA

 

 

Both Ports Deselected,

 

 

 

 

 

 

 

333 MHz

 

 

260

mA

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

 

 

 

 

375 MHz

 

 

290

mA

 

 

f = fmax = 1/tCYC,

 

 

 

 

 

 

 

 

 

 

 

Inputs Static

400 MHz

 

 

300

mA

 

 

 

 

 

 

 

 

AC Input Requirements

Over the operating range [11]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

VDDQ + 0.24

V

VIL

Input LOW Voltage

 

–0.24

VREF – 0.2

V

Notes

15.Power up: Is based on a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω

18.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-06620 Rev. *D

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Contents Features ConfigurationsSelection Guide Functional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1166V18 Logic Block Diagram CY7C1177V18Logic Block Diagram CY7C1168V18 Logic Block Diagram CY7C1170V18Pin Configurations CY7C1166V18 2M xCY7C1177V18 2M x TMSCY7C1168V18 1M x CY7C1170V18 512K xBWS TMS TDIPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Truth Table SRAM#1 SRAM#2Master OperationWrite Cycle Descriptions CommentsRemains unaltered During the Data portion of a write sequenceWrite cycle descriptions of CY7C1170V18 follows DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Shows the tap controller state diagramTAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics TAP Timing and Test ConditionInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristic Maximum RatingsOperating Range AC Input RequirementsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max HighLOW DLL TimingNOP Switching WaveformRead/Write/Deselect Sequence Ordering Information 333 Package Diagram Ball Fbga 13 x 15 x 1.4 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN/KKVTMP