Cypress CY7C1166V18, CY7C1168V18 Capacitance, Thermal Resistance, AC Test Loads and Waveforms

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CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

5

pF

 

 

VDD = 1.8V

 

 

CCLK

Clock Input Capacitance

6

pF

VDDQ = 1.5V

CO

Output Capacitance

 

7

pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Test Conditions

165 FBGA

Unit

Package

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard test methods and

17.2

°C/W

 

(junction to ambient)

procedures for measuring thermal impedance, in

 

 

 

 

accordance with EIA/JESD51.

 

 

ΘJC

Thermal Resistance

4.15

°C/W

 

 

(junction to case)

 

 

 

 

 

 

 

 

AC Test Loads and Waveforms

Figure 6. AC Test loads and Waveforms

VREF = 0.75V

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

DEVICE

 

 

 

 

 

 

 

 

 

UNDER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

 

0.75V

 

 

 

 

 

R = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES[20]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEVICE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UNDER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SLEW RATE= 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

TEST ZQ

 

 

 

 

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

20.Unless otherwise noted, test conditions are based on a signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.

Document Number: 001-06620 Rev. *D

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Contents Configurations FeaturesSelection Guide Functional Description Description 400 MHz 375 MHz 333 MHz 300 MHz UnitLogic Block Diagram CY7C1177V18 Logic Block Diagram CY7C1166V18Logic Block Diagram CY7C1170V18 Logic Block Diagram CY7C1168V18CY7C1166V18 2M x Pin ConfigurationsCY7C1177V18 2M x TMSCY7C1170V18 512K x CY7C1168V18 1M xBWS TMS TDIPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview SRAM#1 SRAM#2 Truth TableMaster OperationComments Write Cycle DescriptionsRemains unaltered During the Data portion of a write sequenceDevice Write cycle descriptions of CY7C1170V18 followsInto the device. D359 remains unaltered Device. D80 and D3518 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode Shows the tap controller state diagram TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Controller Parameter Description Test Conditions Min Max UnitTAP Timing and Test Condition TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicOperating Range AC Input RequirementsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitHigh Parameter Min MaxLOW DLL TimingSwitching Waveform Read/Write/Deselect SequenceNOP Ordering Information 333 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN/KKVTMP