Cypress CY7C1514KV18, CY7C1510KV18 Maximum Ratings, Operating Range, Electrical Characteristics

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CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.5V

DC Input Voltage [11]

–0.5V to V + 0.5V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch up Current

....................................................

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [15]

VDDQ [15]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [12]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 16

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 17

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = −0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.3

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND ≤ VI ≤ VDDQ

 

 

−5

 

5

μA

IOZ

Output Leakage Current

GND ≤ VI ≤ VDDQ, Output Disabled

 

−5

 

5

μA

VREF

Input Reference Voltage [18]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [19]

VDD Operating Supply

VDD = Max,

333 MHz

(x8)

 

 

790

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

790

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

810

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

990

 

 

 

 

 

 

 

 

 

 

 

 

 

300 MHz

(x8)

 

 

730

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

730

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

750

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

910

 

 

 

 

 

 

 

 

 

 

 

 

 

250 MHz

(x8)

 

 

640

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

640

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

650

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

790

 

 

 

 

 

 

 

 

 

 

Notes

15.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

17.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

18.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-00436 Rev. *E

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Contents Features ConfigurationsFunctional Description Cypress Semiconductor Corporation 198 Champion CourtDoff Logic Block Diagram CY7C1510KV18Logic Block Diagram CY7C1525KV18 Logic Block Diagram CY7C1512KV18 Logic Block Diagram CY7C1514KV18Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1510KV18 8M x CY7C1525KV18 8M xCY7C1514KV18 2M x CY7C1512KV18 4M xWPS BWS Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Sram #1 Application ExampleEcho Clocks Truth Table Write Cycle DescriptionsOperation CommentsWrite cycle description table for CY7C1525KV18 follow Write cycle description table for CY7C1514KV18 followDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequencePLL Constraints VDD/ Vddq DoffElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeInput LOW Voltage Vref Document Number 001-00436 Rev. *E AC Electrical CharacteristicsInput High Voltage Vref + Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Parameter Min MaxHigh LOWParameter Min Max Output Times PLL TimingSwitching Waveforms Read/Write/Deselect Sequence 26, 27Ordering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY7C1510KV18, CY7C1514KV18, CY7C1512KV18, CY7C1525KV18 specifications

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