Cypress CY7C1394CV18 TAP Controller State Diagram, State diagram for the TAP controller follows

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CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

TAP Controller State Diagram

The state diagram for the TAP controller follows. [9]

TEST-LOGIC RESET

TEST-LOGIC/ IDLE

1		1	1
1	SELECT	1	SELECT
	DR-SCAN		IR-SCAN
	0		0
	1		1

CAPTURE-DR		CAPTURE-IR
0		0
SHIFT-DR	0	SHIFT-IR	0
1		1
EXIT1-DR	1	EXIT1-IR	1
EXIT1-DR		EXIT1-IR
0		0
PAUSE-DR	0	PAUSE-IR	0
1		1
0		0
EXIT2-DR		EXIT2-IR
1		1
UPDATE-DR		UPDATE-IR
1		1
0		0

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 001-07162 Rev. *C

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1392CV18CLK 512K Logic Block Diagram CY7C1393CV18Logic Block Diagram CY7C1394CV18 Array Gen Read Data Reg ControlCY7C1392CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1992CV18 2M xCY7C1393CV18 1M x CY7C1394CV18 512K xSynchronous Read/Write input. When Pin DefinitionsPin Name Pin Description Is referenced with respect to Power supply inputs to the core of the devicePower supply inputs for the outputs of the device TDO for JtagFunctional Overview Application Example Shows four DDR-II SIO used in an applicationOperation Truth TableWrite Cycle Descriptions Comments Device Write cycle description table for CY7C1992CV18 follows Write cycle description table for CY7C1394CV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 001-07162 Rev. *C AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max Output Times DLL TimingSwitching Waveforms BurstOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions