Cypress CY7C1393CV18, CY7C1992CV18 manual AC Electrical Characteristics, Input High Voltage Vref +

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CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [12]

Parameter	Description	Test Conditions			Min	Typ	Max	Unit
IDD [19]	VDD Operating Supply	VDD = Max,	200 MHz	(x8)			575	mA
		IOUT = 0 mA,
		IOUT = 0 mA,		(x9)			575
		f = fMAX = 1/tCYC
		f = fMAX = 1/tCYC		(x18)			600
				(x18)			600

				(x36)			630

			167 MHz	(x8)			485	mA

				(x9)			490

				(x18)			500

				(x36)			540

ISB1	Automatic Power Down	Max VDD,	300 MHz	(x8)			275	mA
	Current	Both Ports Deselected,
	Current	Both Ports Deselected,		(x9)			275
		VIN ≥ VIH or VIN ≤ VIL		(x9)			275


		f = fMAX = 1/tCYC,		(x18)			285
		Inputs Static
		Inputs Static		(x36)			300
				(x36)			300

			278 MHz	(x8)			265	mA

				(x9)			265

				(x18)			275

				(x36)			290

			250 MHz	(x8)			255	mA

				(x9)			255

				(x18)			260

				(x36)			275

			200 MHz	(x8)			245	mA

				(x9)			245

				(x18)			250

				(x36)			260

			167 MHz	(x8)			240	mA

				(x9)			240

				(x18)			245

				(x36)			255

AC Electrical Characteristics

Over the Operating Range [11]

Parameter	Description	Test Conditions	Min	Typ	Max	Unit
VIH	Input HIGH Voltage		VREF + 0.2	–	–	V
VIL	Input LOW Voltage		–	–	VREF – 0.2	V

Document #: 001-07162 Rev. *C

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1392CV18 CLKDoff Logic Block Diagram CY7C1394CV18 Logic Block Diagram CY7C1393CV18512K Array Gen Read Data Reg ControlBall Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1392CV18 2M x CY7C1992CV18 2M xCY7C1394CV18 512K x CY7C1393CV18 1M xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write input. When Power supply inputs for the outputs of the device Power supply inputs to the core of the deviceIs referenced with respect to TDO for JtagFunctional Overview Shows four DDR-II SIO used in an application Application ExampleWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1394CV18 follows Write cycle description table for CY7C1992CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 001-07162 Rev. *C Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History