Cypress CY7C1393CV18, CY7C1992CV18, CY7C1394CV18, CY7C1392CV18 manual Switching Waveforms, Burst

Page 25

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [27, 28, 29]

NOP

READ

READ

WRITE

WRITE

READ

NOP

 

 

(burst of 2)

(burst of 2)

(burst of 2)

(burst of 2)

(burst of 2)

 

 

1

2

3

4

5

6

7

8

K

K

LD

R/W

A

D

Q

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKH

 

tKL

 

tCYC

tKHKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSC

 

A0

 

A1

A2

 

A3

 

A4

 

 

t

SA

t

HA

 

tHD

 

 

tHD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSD

 

 

tSD

 

 

 

 

 

 

 

 

D20

D21

D30

D31

 

 

 

 

 

Q00

Q01

Q10

Q11

 

Q40

Q41

 

 

 

t KHCH

tCLZ

tCQD

tDOH

 

 

 

 

 

 

 

 

 

 

 

tKHCH

 

 

 

tCO

tCQDOH

 

 

tCHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C#

CQ

CQ#

tCQOH

tCQOH

tCCQO

tKH

 

tKL

tCCQO

tCQH

tCYC

tCQHCQH

tKHKH

DON’T CARE

UNDEFINED

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document #: 001-07162 Rev. *C

Page 25 of 30

[+] Feedback

Page 24 Page 26
Image 25
Page 24 Page 26
Contents Configurations FeaturesFunctional Description Selection GuideCLK Logic Block Diagram CY7C1392CV18Doff Logic Block Diagram CY7C1394CV18 Logic Block Diagram CY7C1393CV18512K Array Gen Read Data Reg ControlBall Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1392CV18 2M x CY7C1992CV18 2M xCY7C1394CV18 512K x CY7C1393CV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write input. When Power supply inputs for the outputs of the device Power supply inputs to the core of the deviceIs referenced with respect to TDO for JtagFunctional Overview Shows four DDR-II SIO used in an application Application ExampleWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1394CV18 follows Write cycle description table for CY7C1992CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document # 001-07162 Rev. *C Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History
Top Page Image Contents