Cypress CY7C1393CV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1392CV18	CY7C1992CV18	CY7C1393CV18	CY7C1394CV18	Description
		CY7C1392CV18	CY7C1992CV18	CY7C1393CV18	CY7C1394CV18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010100010000101	11010100010001101	11010100010010101	11010100010100101	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	107

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document #: 001-07162 Rev. *C

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1392CV18CLK Logic Block Diagram CY7C1394CV18 Logic Block Diagram CY7C1393CV18512K Array Gen Read Data Reg ControlBall Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1392CV18 2M x CY7C1992CV18 2M xCY7C1394CV18 512K x CY7C1393CV18 1M xSynchronous Read/Write input. When Pin DefinitionsPin Name Pin Description Power supply inputs for the outputs of the device Power supply inputs to the core of the deviceIs referenced with respect to TDO for JtagFunctional Overview Shows four DDR-II SIO used in an application Application ExampleWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1394CV18 follows Write cycle description table for CY7C1992CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 001-07162 Rev. *C AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions