Cypress CY7C1394CV18, CY7C1992CV18, CY7C1393CV18, CY7C1392CV18 manual Ordering Information

Page 26

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1392CV18-300BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992CV18-300BZC

	CY7C1393CV18-300BZC

	CY7C1394CV18-300BZC

	CY7C1392CV18-300BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-300BZXC

	CY7C1393CV18-300BZXC

	CY7C1394CV18-300BZXC

	CY7C1392CV18-300BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992CV18-300BZI

	CY7C1393CV18-300BZI

	CY7C1394CV18-300BZI

	CY7C1392CV18-300BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-300BZXI

	CY7C1393CV18-300BZXI

	CY7C1394CV18-300BZXI

278	CY7C1392CV18-278BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992CV18-278BZC

	CY7C1393CV18-278BZC

	CY7C1394CV18-278BZC

	CY7C1392CV18-278BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-278BZXC

	CY7C1393CV18-278BZXC

	CY7C1394CV18-278BZXC

	CY7C1392CV18-278BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992CV18-278BZI

	CY7C1393CV18-278BZI

	CY7C1394CV18-278BZI

	CY7C1392CV18-278BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-278BZXI

	CY7C1393CV18-278BZXI

	CY7C1394CV18-278BZXI

Document #: 001-07162 Rev. *C

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1392CV18CLK 512K Logic Block Diagram CY7C1393CV18Logic Block Diagram CY7C1394CV18 Array Gen Read Data Reg ControlCY7C1392CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1992CV18 2M xCY7C1393CV18 1M x CY7C1394CV18 512K xSynchronous Read/Write input. When Pin DefinitionsPin Name Pin Description Is referenced with respect to Power supply inputs to the core of the devicePower supply inputs for the outputs of the device TDO for JtagFunctional Overview Application Example Shows four DDR-II SIO used in an applicationOperation Truth TableWrite Cycle Descriptions CommentsDevice Write cycle description table for CY7C1992CV18 followsWrite cycle description table for CY7C1394CV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 001-07162 Rev. *C AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga Unit High Switching Characteristics Parameter Min Max LOWParameter Min Max Output Times DLL TimingSwitching Waveforms BurstOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions