Cypress CY7C1992CV18 Pin Configuration, Ball Fbga 13 x 15 x 1.4 mm Pinout, CY7C1392CV18 2M x

Page 4

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Pin Configuration

The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. [1]

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1392CV18 (2M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

CQ

R/W

NWS1

K

NC/144M

LD

A

NC/36M

CQ

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1992CV18 (2M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

NC/36M

CQ

CQ

R/W

K

LD

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

Document #: 001-07162 Rev. *C

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Contents Features ConfigurationsFunctional Description Selection GuideCLK Logic Block Diagram CY7C1392CV18Doff Logic Block Diagram CY7C1393CV18 Logic Block Diagram CY7C1394CV18512K Array Gen Read Data Reg ControlPin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1392CV18 2M x CY7C1992CV18 2M xCY7C1393CV18 1M x CY7C1394CV18 512K xPin Name Pin Description Pin DefinitionsSynchronous Read/Write input. When Power supply inputs to the core of the device Power supply inputs for the outputs of the deviceIs referenced with respect to TDO for JtagFunctional Overview Application Example Shows four DDR-II SIO used in an applicationTruth Table Write Cycle DescriptionsOperation CommentsWrite cycle description table for CY7C1992CV18 follows Write cycle description table for CY7C1394CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document # 001-07162 Rev. *C Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Parameter Min MaxHigh LOWParameter Min Max Output Times DLL TimingSwitching Waveforms BurstOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History