Cypress CY7C1392BV18, CY7C1992BV18, CY7C1393BV18 Power Up Sequence in DDR-II Sram, DLL Constraints

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CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18

Power Up Sequence in DDR-II SRAM

DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

❐Drive DOFF HIGH.

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency.

■Provide stable DOFF (HIGH), power and clock (K, K) for 1024 cycles to lock the DLL.

K

K

VDD/ VDDQ

DOFF

Figure 3. Power Up Waveforms

~ ~

	~ ~
Unstable Clock	> 1024 Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )

Fix High (or tie to VDDQ)

Document #: 38-05623 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1392BV18Doff Array Gen Read Data Reg Control Logic Block Diagram CY7C1393BV18Logic Block Diagram CY7C1394BV18 512KCY7C1992BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1392BV18 2M xCY7C1394BV18 512K x CY7C1393BV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Is Referenced with Respect toFunctional Overview Shows four DDR-II SIO used in an application Application ExampleComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1992BV18 followsWrite cycle description table for CY7C1394BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document # 38-05623 Rev. *D Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramSYT Document HistoryNXR USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS