Cypress CY7C1392BV18, CY7C1992BV18 Is Referenced with Respect to, TDO for Jtag, TCK Pin for Jtag

Page 7

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Pin Definitions (continued)

Pin Name

IO

Pin Description

CQ

Echo Clock

CQ is Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks is shown in the Switching Characteristics on page 23.

Echo Clock

is Referenced with Respect to

. This is a free-running clock and is synchronized to the input clock

CQ

CQ

C

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks is shown in the Switching Characteristics on page 23.

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

DOFF

in the DLL turned off operation differs from those listed in this data sheet.

TDO

Output

TDO for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/36M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/72M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

N/A

Not Connected to the Die. Can be tied to any voltage level.

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and AC

Reference

measurement points.

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

VSS

Ground

Ground for the Device.

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document #: 38-05623 Rev. *D

Page 7 of 31

[+] Feedback

Image 7

Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1392BV18Doff Array Gen Read Data Reg Control Logic Block Diagram CY7C1393BV18Logic Block Diagram CY7C1394BV18 512KCY7C1992BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1392BV18 2M xCY7C1394BV18 512K x CY7C1393BV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Is Referenced with Respect toFunctional Overview Shows four DDR-II SIO used in an application Application ExampleComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1992BV18 followsWrite cycle description table for CY7C1394BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document # 38-05623 Rev. *D Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramSYT Document HistoryNXR USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS