Cypress CY7C1394BV18, CY7C1992BV18, CY7C1393BV18, CY7C1392BV18 manual Document History, Syt, Nxr

Page 30

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Document History Page

Document Title: CY7C1392BV18/CY7C1992BV18/CY7C1393BV18/CY7C1394BV18, 18-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

Document Number: 38-05623

Rev.

ECN No.

Submission

Orig, of

Description of Change

 

 

Date

Change

 

**

252474

See ECN

SYT

New data sheet

 

 

 

 

 

*A

325581

See ECN

SYT

Removed CY7C1394BV18 from the title

 

 

 

 

Included 300-MHz Speed Bin

 

 

 

 

Added Industrial Temperature Grade

 

 

 

 

Replaced TBDs for IDD and ISB1 specs

 

 

 

 

Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51°C/W and ΘJC

 

 

 

 

= 5.91°C/W

 

 

 

 

Replaced TBDs in the Capacitance Table for the 165 FBGA Package

 

 

 

 

Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D

 

 

 

 

(13 x 15 x 1.4 mm)

 

 

 

 

Added Lead-Free Product Information

 

 

 

 

Updated the Ordering Information by Shading and Unshading MPNs as per availability

*B

413997

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Added CY7C1992BV18 part number to the title

 

 

 

 

Added 278-MHz speed Bin

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North

 

 

 

 

First Street” to “198 Champion Court”

 

 

 

 

Changed C/C Pin Description in the features section and Pin Description

 

 

 

 

Added power-up sequence details and waveforms

 

 

 

 

Added foot notes #15, 16, 17 on page# 18

 

 

 

 

Replaced Three-state with Tri-state

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage Current on

 

 

 

 

page# 19

 

 

 

 

Modified the IDD and ISB values

 

 

 

 

Modified test condition in Footnote #18 on page# 19 from VDDQ < VDD to

 

 

 

 

VDDQ < VDD

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated the Ordering Information

*C

472384

See ECN

NXR

Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD

 

 

 

 

to Alternately, this pin can be connected directly to VDDQ

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD

 

 

 

 

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH

 

 

 

 

from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power-Up waveform

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C

 

 

 

 

to +85°C to –55°C to +125°C

 

 

 

 

Added additional notes in the AC parameter section

 

 

 

 

Modified AC Switching Waveform

 

 

 

 

Corrected the typo In the AC Switching Characteristics Table

 

 

 

 

Updated the Ordering Information Table

Document #: 38-05623 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1392BV18 CLKDoff 512K Logic Block Diagram CY7C1393BV18Logic Block Diagram CY7C1394BV18 Array Gen Read Data Reg ControlCY7C1392BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1992BV18 2M xCY7C1393BV18 1M x CY7C1394BV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Is Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Application Example Shows four DDR-II SIO used in an applicationOperation Truth TableWrite Cycle Descriptions CommentsDevice Write cycle description table for CY7C1992BV18 followsWrite cycle description table for CY7C1394BV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 38-05623 Rev. *D Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max Output Times DLL TimingSwitching Waveforms BurstOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History SYTNXR VKN/PYRS Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions USB
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