Cypress CY7C1392BV18 Logic Block Diagram CY7C1393BV18, Logic Block Diagram CY7C1394BV18, 512K

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Logic Block Diagram (CY7C1393BV18)

D[17:0]

19

A(18:0)

K

K

DOFF

R/W

VREF

LD

BWS[1:0]

18
		Write	Write
Address		Data Reg	Data Reg
	Decode	512K x	512K x
Register
CLK	Write Add.	18 Array	18 Array
Gen.

Read Data Reg.

	36	18
Control		18
Logic

Read Add. Decode

Reg.

Reg.

LD

Control R/W

Logic

C

C

		CQ
Reg. 18		CQ
18	18	Q[17:0]

Logic Block Diagram (CY7C1394BV18)

D[35:0]

18

A(17:0)

K

K

DOFF

R/W

VREF

LD

BWS[3:0]

36
		Write	Write
Address		Data Reg	Data Reg
	Decode	256K x	256K x
Register
CLK	Write Add.	36 Array	36 Array
Gen.

Read Data Reg.

	72	36
Control		36
Logic

Read Add. Decode

Reg.

Reg.

LD

Control R/W

Logic

C

C

		CQ
Reg. 36		CQ
36	36	Q[35:0]

Document #: 38-05623 Rev. *D Page 3 of 31

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