Cypress CY7C1992BV18, CY7C1392BV18 manual CY7C1393BV18 1M x, CY7C1394BV18 512K x

Page 5

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Pin Configuration (continued)

The pin configuration for CY7C1392BV18, CY7C1992BV18, CY7C1393BV18, and CY7C1394BV18 follows. [1]

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1393BV18 (1M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

NC/36M

CQ

R/W

BWS1

K

NC/288M

LD

A

NC/72M

CQ

B

NC

Q9

D9

A

NC

K

0

A

NC

NC

Q8

BWS

C

NC

NC

D10

VSS

A

A

A

VSS

NC

Q7

D8

D

NC

D11

Q10

VSS

VSS

VSS

VSS

VSS

NC

NC

D7

E

NC

NC

Q11

VDDQ

VSS

VSS

VSS

VDDQ

NC

D6

Q6

F

NC

Q12

D12

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

Q5

G

NC

D13

Q13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

D5

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

D14

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q4

D4

K

NC

NC

Q14

VDDQ

VDD

VSS

VDD

VDDQ

NC

D3

Q3

L

NC

Q15

D15

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q2

M

NC

NC

D16

VSS

VSS

VSS

VSS

VSS

NC

Q1

D2

N

NC

D17

Q16

VSS

A

A

A

VSS

NC

NC

D1

P

NC

NC

Q17

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1394BV18 (512K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

NC/72M

CQ

R/W

BWS2

K

BWS1

LD

NC/36M

NC/144M

CQ

B

Q27

Q18

D18

A

3

K

0

A

D17

Q17

Q8

BWS

BWS

C

D27

Q28

D19

VSS

A

A

A

VSS

D16

Q7

D8

D

D28

D20

Q19

VSS

VSS

VSS

VSS

VSS

Q16

D15

D7

E

Q29

D29

Q20

VDDQ

VSS

VSS

VSS

VDDQ

Q15

D6

Q6

F

Q30

Q21

D21

VDDQ

VDD

VSS

VDD

VDDQ

D14

Q14

Q5

G

D30

D22

Q22

VDDQ

VDD

VSS

VDD

VDDQ

Q13

D13

D5

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

D31

Q31

D23

VDDQ

VDD

VSS

VDD

VDDQ

D12

Q4

D4

K

Q32

D32

Q23

VDDQ

VDD

VSS

VDD

VDDQ

Q12

D3

Q3

L

Q33

Q24

D24

VDDQ

VSS

VSS

VSS

VDDQ

D11

Q11

Q2

M

D33

Q34

D25

VSS

VSS

VSS

VSS

VSS

D10

Q1

D2

N

D34

D26

Q25

VSS

A

A

A

VSS

Q10

D9

D1

P

Q35

D35

Q26

A

A

C

A

A

Q9

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Document #: 38-05623 Rev. *D

Page 5 of 31

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Contents Configurations FeaturesFunctional Description Selection Guide Doff Logic Block Diagram CY7C1392BV18 CLK Logic Block Diagram CY7C1394BV18 Logic Block Diagram CY7C1393BV18512K Array Gen Read Data Reg ControlBall Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1392BV18 2M x CY7C1992BV18 2M xCY7C1394BV18 512K x CY7C1393BV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Shows four DDR-II SIO used in an application Application ExampleWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1394BV18 follows Write cycle description table for CY7C1992BV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05623 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR Document HistorySYT Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/PYRS USB