Cypress CY7C1392BV18, CY7C1393BV18 Write cycle description table for CY7C1992BV18 follows, Device

Page 11

CY7C1392BV18, CY7C1992BV18

CY7C1393BV18, CY7C1394BV18

Write Cycle Descriptions

The write cycle description table for CY7C1992BV18 follows. [2, 8]

BWS0

K

K

 

L

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1394BV18 follows. [2, 8]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

L

 

L

 

L

 

L

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

L

 

H

 

H

 

H

L–H

 

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

L

 

H

 

H

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

H

 

L

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

L

 

H

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

H

 

L

L–H

 

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05623 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1392BV18CLK Array Gen Read Data Reg Control Logic Block Diagram CY7C1393BV18Logic Block Diagram CY7C1394BV18 512KCY7C1992BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1392BV18 2M xCY7C1394BV18 512K x CY7C1393BV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Is Referenced with Respect toFunctional Overview Shows four DDR-II SIO used in an application Application ExampleComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1992BV18 followsWrite cycle description table for CY7C1394BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05623 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR Document HistorySYT USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS