Cypress CY7C1518JV18, CY7C1520JV18 manual Maximum Ratings, DC Electrical Characteristics

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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [11]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M 3015)....

>2001V

Latch Up Current

....................................................

 

>200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [15]

VDDQ [15]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [12]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 16

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 17

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.3

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

5

 

5

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

5

 

5

μA

VREF

Input Reference Voltage [18]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [19]

VDD Operating Supply

VDD = Max,

300 MHz

(x8)

 

 

1035

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

1035

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

1045

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1055

 

 

 

 

250 MHz

(x8)

 

 

800

mA

 

 

 

 

(x9)

 

 

800

 

 

 

 

 

(x18)

 

 

800

 

 

 

 

 

(x36)

 

 

900

 

ISB1

Automatic Power Down

Max VDD,

300 MHz

(x8)

 

 

410

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

 

 

(x9)

 

 

410

 

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

(x18)

 

 

415

 

 

 

f = fMAX = 1/tCYC, Inputs

 

 

 

 

 

 

Static

 

(x36)

 

 

415

 

 

 

 

250 MHz

(x8)

 

 

380

mA

 

 

 

 

(x9)

 

 

380

 

 

 

 

 

(x18)

 

 

380

 

 

 

 

 

(x36)

 

 

380

 

Notes

15.Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-12559 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1516JV18 Logic Block Diagram CY7C1527JV18Doff CLKBWS Logic Block Diagram CY7C1518JV18Logic Block Diagram CY7C1520JV18 Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1516JV18 8M x CY7C1527JV18 8M xCY7C1518JV18 4M x CY7C1520JV18 2M xPin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagDDR Operation Single Clock ModeFunctional Overview Application Example Depth ExpansionProgrammable Impedance Echo ClocksNWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitDLL Timing Cypress Consortium Description 300 MHz 250 MHz UnitParameter Min Max Switching Waveforms NOPRead NOP Write ReadOrdering Information Package Diagram Ball Fbga 15 x 17 x 1.40 mmREV ECN no Issue ORIG. Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions