Cypress CY7C1527JV18, CY7C1518JV18, CY7C1520JV18 manual Sales, Solutions, and Legal Information

Page 26

CY7C1516JV18, CY7C1527JV18

CY7C1518JV18, CY7C1520JV18

Document History Page

Document Title: CY7C1516JV18/CY7C1527JV18/CY7C1518JV18/CY7C1520JV18, 72-Mbit DDR-II SRAM 2-Word

Burst Architecture

Document Number: 001-12559

REV.

ECN NO.

ISSUE

ORIG. OF

DESCRIPTION OF CHANGE

DATE

CHANGE

 

 

 

 

 

 

 

 

**

808457

See ECN

VKN

New Data Sheet

 

 

 

 

 

*A

1273883

See ECN

VKN

Removed tSD footnote

 

 

 

 

Updated Logic block diagram for x18 and x36 parts

*B

1462589

See ECN

VKN/AESA

Converted from preliminary to final

 

 

 

 

Updated IDD/ISB specs

 

 

 

 

Changed DLL minimum operating frequency from 80MHz to 120MHz

 

 

 

 

Changed tCYC max spec to 8.4ns

*C

2189567

See ECN

VKN/AESA

Minor Change-Moved to the external web

 

 

 

 

 

*D

2521072

06/25/08

NXR/PYRS

Updated Logic block diagram, Changed the pin name from VSS/144M and VSS/288M

 

 

 

 

to NC/144M and NC/288M respectively in Pin Definition table, Changed JTAG ID

 

 

 

 

[31:29] from 001 to 000, Updated power up sequence waveform and its description,

 

 

 

 

Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C

 

 

 

 

to +125°C” in the “Maximum Ratings “ on page 20, Added footnote #19 related to

 

 

 

 

IDD, Changed ΘJA spec from 16.2 to 16.3, Changed ΘJC spec from 2.3 to 2.1.

Sales, Solutions, and Legal Information

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© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-12559 Rev. *D

Revised June 25, 2008

Page 26 of 26

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1516JV18Logic Block Diagram CY7C1527JV18 CLKBWS Logic Block Diagram CY7C1518JV18Logic Block Diagram CY7C1520JV18 CY7C1516JV18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1527JV18 8M xCY7C1518JV18 4M x CY7C1520JV18 2M xPin Definitions Pin Name Pin DescriptionTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagDDR Operation Single Clock ModeFunctional Overview Programmable Impedance Application ExampleDepth Expansion Echo ClocksNWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Thermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitDLL Timing Cypress Consortium Description 300 MHz 250 MHz UnitParameter Min Max Read Switching WaveformsNOP NOP Write ReadOrdering Information Package Diagram Ball Fbga 15 x 17 x 1.40 mmREV ECN no Issue ORIG. Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions