Cypress CY8C24423A manual Register Map Bank 1 Table Configuration Space, Name Addr 1,Hex Access

Page 12

CY8C24223A, CY8C24423A

Table 6. Register Map Bank 0 Table: User Space (continued)

Name

Addr (0,Hex)

Access

Name

Addr (0,Hex)

Access

Name

Addr (0,Hex)

Access

Name

Addr (0,Hex)

Access

 

 

 

 

 

 

 

 

 

 

 

 

DCB03DR2

2E

RW

 

6E

 

 

AE

 

ACC_DR3

EE

RW

 

 

 

 

 

 

 

 

 

 

 

 

DCB03CR0

2F

#

 

6F

 

 

AF

 

ACC_DR2

EF

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

ACB00CR3

70

RW

RDI0RI

B0

RW

 

F0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

ACB00CR0

71

RW

RDI0SYN

B1

RW

 

F1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

ACB00CR1

72

RW

RDI0IS

B2

RW

 

F2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

ACB00CR2

73

RW

RDI0LT0

B3

RW

 

F3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

ACB01CR3

74

RW

RDI0LT1

B4

RW

 

F4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

 

ACB01CR0

75

RW

RDI0RO0

B5

RW

 

F5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

 

ACB01CR1

76

RW

RDI0RO1

B6

RW

 

F6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

37

 

ACB01CR2

77

RW

 

B7

 

CPU_F

F7

RL

 

 

 

 

 

 

 

 

 

 

 

 

 

38

 

 

78

 

 

B8

 

 

F8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

 

 

79

 

 

B9

 

 

F9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3A

 

 

7A

 

 

BA

 

 

FA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3B

 

 

7B

 

 

BB

 

 

FB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3C

 

 

7C

 

 

BC

 

 

FC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3D

 

 

7D

 

 

BD

 

 

FD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3E

 

 

7E

 

 

BE

 

CPU_SCR1

FE

#

 

 

 

 

 

 

 

 

 

 

 

 

 

3F

 

 

7F

 

 

BF

 

CPU_SCR0

FF

#

 

 

 

 

 

 

 

 

 

 

 

 

Blank fields are Reserved and must not be accessed.

 

 

# Access is bit specific.

 

 

 

 

Table 7. Register Map Bank 1 Table: Configuration Space

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

Name

Addr (1,Hex)

Access

PRT0DM0

00

RW

 

40

 

ASC10CR0

80

RW

 

C0

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT0DM1

01

RW

 

41

 

ASC10CR1

81

RW

 

C1

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT0IC0

02

RW

 

42

 

ASC10CR2

82

RW

 

C2

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT0IC1

03

RW

 

43

 

ASC10CR3

83

RW

 

C3

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1DM0

04

RW

 

44

 

ASD11CR0

84

RW

 

C4

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1DM1

05

RW

 

45

 

ASD11CR1

85

RW

 

C5

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1IC0

06

RW

 

46

 

ASD11CR2

86

RW

 

C6

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT1IC1

07

RW

 

47

 

ASD11CR3

87

RW

 

C7

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2DM0

08

RW

 

48

 

 

88

 

 

C8

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2DM1

09

RW

 

49

 

 

89

 

 

C9

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2IC0

0A

RW

 

4A

 

 

8A

 

 

CA

 

 

 

 

 

 

 

 

 

 

 

 

 

PRT2IC1

0B

RW

 

4B

 

 

8B

 

 

CB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C

 

 

4C

 

 

8C

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D

 

 

4D

 

 

8D

 

 

CD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E

 

 

4E

 

 

8E

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0F

 

 

4F

 

 

8F

 

 

CF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

50

 

ASD20CR0

90

RW

GDI_O_IN

D0

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

51

 

ASD20CR1

91

RW

GDI_E_IN

D1

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

52

 

ASD20CR2

92

RW

GDI_O_OU

D2

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

53

 

ASD20CR3

93

RW

GDI_E_OU

D3

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

54

 

ASC21CR0

94

RW

 

D4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

55

 

ASC21CR1

95

RW

 

D5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

56

 

ASC21CR2

96

RW

 

D6

 

 

 

 

 

 

 

 

 

 

 

 

 

Blank fields are Reserved and must not be accessed.

 

 

# Access is bit specific.

 

 

 

 

Document Number: 3-12029 Rev. *E

Page 12 of 31

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Contents Features Logic Block DiagramCypress Semiconductor Corporation 198 Champion Court PSoC Functional Overview PSoC CoreDigital System Analog System Block Diagram Analog SystemPSoC Device Characteristics PSoC Device CharacteristicsGetting Started Additional System ResourcesDevelopment Tools PSoC Designer Software SubsystemsDevice Editor Design BrowserDesigning with User Modules Hardware ToolsApplication Editor Document Conventions Acronyms UsedUnits of Measure Numeric NamingPinouts Pin Part PinoutPin Part Pinout Ssop Type Description Digital Analog Name Active high external reset with internal pull Pin Part Pinout Ssop Type Description Digi- Ana NameRegister Reference Register ConventionsRegister Mapping Tables Abbreviations UsedName Addr 0,Hex Access Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space Name Addr 1,Hex AccessCY8C24223A, CY8C24423A Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Absolute Maximum Ratings Symbol Description Min Typ UnitsOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Electrical Characteristics DC General Purpose IO SpecificationsDC Chip-Level Specifications DC Gpio Specifications Symbol Description Min Typ Max UnitsDC Operational Amplifier Specifications PsrroaDC Low Power Comparator Specifications DC Analog Output Buffer SpecificationsPsrrob DC Analog Reference Specifications CT Block Power = High RefHi = Vdd/2 + BandGapRef Control Power = High DC Analog PSoC Block Specifications DC POR and LVD SpecificationsDC Programming Specifications AC Electrical Characteristics AC Chip-Level SpecificationsDC24M Enable Gain32K Select AC General Purpose IO Specifications AC Gpio Specifications Symbol Description Min Typ Max UnitsAC Operational Amplifier Specifications BwoaAC Low Power Comparator Specifications Typical Agnd Noise with P24 BypassAC Digital Block Specifications CrcprsSpim SpisAC Analog Output Buffer Specifications AC External Clock SpecificationsAC Programming Specifications BwobAC I2C Specifications SDASCL Packaging Information Pin 210-Mil SsopCapacitance on Crystal Pins Solder Reflow Peak TemperatureTypical Package Capacitance on Crystal Pins Thermal ImpedancesOrdering Information Ordering Code DefinitionsSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History Orig. Submission Description of Change Date