Cypress CY7C63413C, CY7C63613C, CY7C63513C manual Switching Characteristics

Page 26

CY7C63413C

CY7C63513C

CY7C63613C

DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C (continued)

 

 

Parameter

 

 

Min.

 

Max.

Unit

 

Conditions

VH

Input Hysteresis Voltage

 

 

6%

 

12%

VCC

 

All ports, HIGH to LOW edge

Iol

Sink Current

 

 

7.2

 

16.5

mA

 

Port 3, Vout = 1.0V (note 4)

Iol

Sink Current

 

 

3.5

 

10.6

mA

 

Port 0,1,2, Vout = 2.0V (note 4)

Ioh

Source Current

 

 

1.4

 

7.5

 

mA

 

Voh = 2.4V (all ports 0,1,2,3) (note 4)

 

 

DAC Interface

 

 

 

 

 

 

 

 

 

 

 

Rup

Pull-up Resistance

 

 

8.0K

 

20.0K

Ohms

 

(note 14)

Isink0(0)

DAC[7:2] Sink Current (0)[15]

 

 

0.1

 

0.3

 

mA

 

Vout = 2.0 VDC (note 5)

Isink0(F)

DAC[7:2] Sink Current (F)[15]

 

 

0.5

 

1.5

 

mA

 

Vout = 2.0 DC (note 5)

Isink1(0)

DAC[1:0] Sink Current (0)[15]

 

 

1.6

 

4.8

 

mA

 

Vout = 2.0 VDC (note 5)

Isink1(F)

DAC[1:0] Sink Current (F)[15]

 

 

8

 

24

 

mA

 

Vout = 2.0 VDC (note 5)

Irange

Programmed Isink Ratio: max/min

 

 

4

 

6

 

 

 

Vout = 2.0 VDC (notes 5,12)

Ilin

Differential Nonlinearity

 

 

 

 

 

0.5

 

lsb

 

Any pin (note 10)

tsink

Current Sink Response Time

 

 

 

 

 

0.8

 

∝s

 

Full scale transition

Tratio

Tracking Ratio DAC[1:0] to DAC[7:2]

 

 

14

 

21

 

 

 

Vout = 2.0V (note 11)

Switching Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Description

Min.

 

 

Max.

 

Unit

 

Conditions

 

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

Input Clock Cycle Time

165.0

 

 

168.3

 

ns

 

 

 

tCH

Clock HIGH Time

0.45 tCYC

 

 

 

 

ns

 

 

 

tCL

Clock LOW Time

0.45 tCYC

 

 

 

 

ns

 

 

 

 

USB Driver

Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tr

Transition Rise Time

75

 

 

 

 

 

 

ns

CLoad = 50 pF[5, 9]

 

tr

Transition Rise Time

 

 

 

 

300

 

ns

CLoad = 600 pF 5, 9]

 

t

f

Transition Fall Time

75

 

 

 

 

 

 

ns

CLoad = 50 pF[5, 9]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

f

Transition Fall Time

 

 

 

 

300

 

ns

CLoad = 600 pF[5, 9]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

rfm

Rise/Fall Time Matching

80

 

 

 

125

 

%

t /t [5, 9]

 

 

 

 

 

 

 

 

 

 

 

r f

 

Vcrs

Output Signal Crossover Voltage

1.3

 

 

 

2.0

 

V

Notes 5 and 9

 

 

USB Data

Timing

 

 

 

 

 

 

 

 

 

 

 

tdrate

Low Speed Data Rate

1.4775

 

1.5225

 

Mbs

Ave. Bit Rate (1.5 Mb/s ± 1.5%)

 

t

djr1

Receiver Data Jitter Tolerance

–75

 

 

75

 

ns

To Next Transition[13]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

djr2

Receiver Data Jitter Tolerance

–45

 

 

45

 

ns

For Paired Transitions[13]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tdeop

Differential to EOP Transition Skew

–40

 

 

100

 

ns

Note 6

 

teopr1

EOP Width at Receiver

330

 

 

 

 

 

ns

Rejects as EOP[13]

 

teopr2

EOP Width at Receiver

675

 

 

 

 

 

ns

Accepts as EOP[13]

 

teopt

Source EOP Width

1.25

 

 

1.50

 

∝s

 

 

 

tudj1

Differential Driver Jitter

–95

 

 

95

 

ns

To next transition, Figure 12

 

tudj2

Differential Driver Jitter

–150

 

 

150

 

ns

To paired transition, Figure 12

 

Notes:

9. Per Table 7-7 of revision 1.1 of USB specification, for CLOAD of 50–600 pF.

10. Measured as largest step size vs. nominal according to measured full scale and zero programmed values.

11. Tratio = Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed.

12. Irange: Isinkn(15)/ Isinkn(0) for the same pin.

13. Measured at crossover point of differential data signals.

14. Limits total bus capacitance loading (CLOAD) to 400 pF per section 7.1.5 of revision 1.1 of USB specification.

15. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused pins.

Document #: 38-08027 Rev. *B

Page 26 of 32

[+] Feedback

Page 25 Page 27
Image 26
Page 25 Page 27
Contents Cypress Semiconductor Corporation FeaturesFunctional Overview CY7C63413C CY7C63513C CY7C63613C Logic Block Diagram Pin Definitions Programming ModelMOV A,DSPINIT Bit Data Stack Pointer DSPAddress Modes Buttons EQU 10h MOV A,buttonsInstruction Set Summary Operand Opcode CyclesReserved Memory OrganizationProgram Memory Organization Program Memory begins hereData Memory Organization Register Name Address Read/Write Function Register SummaryO Register Summary USB Address A, Endpoint 0 counter registerReset ClockingAddr Port 1 Data General Purpose I/O PortsPin Addr Port 2 DataGpio Configuration Port Port 0 Interrupt EnableGpio Interrupt Enable Ports Addr Port 0 Interrupt EnableDAC Port + defaultAddr Gpio Configuration Register Cmos OutputDAC Port Interrupts DAC Port Interrupt EnableAddr DAC Port Interrupt Enable DAC Isink RegistersUSB Serial Interface Engine SIE USB Device Data 0/1 USB Device Counter RegistersAddr 0x11, 0x13 USB Device Counter Registers Byte countAddr Timer Register LSB Bit Free-running TimerTimer LSB Timer Register Timer MSB Timer Register Addr Timer Register MSBInterrupts Global Interrupt Enable Register AddrUSB End Point Interrupt Enable Register Addr Gpio DACInterrupt Vector Number ROM Address Function Interrupt VectorsInterrupt Vector Assignments Interrupt LatencyEncoding USB Register Mode EncodingTruth Tables NAKWhat the SIE does to Mode bits PID Status bits Interrupt? EncodingControl Write Set End Point ModeSetup Packet if accepting Control ReadOut endpoint Parameter Min Max Unit Conditions General Power-On ResetAbsolute Maximum Ratings USB InterfaceSwitching Characteristics Differential Data Lines Package Package Type Operating Size Ordering InformationOrdering Code RangeDie Pad Locations DIe Pad Locations in microns Pad # Pin NameLead 600-Mil Molded DIP P2 Package DiagramsLead Shrunk Small Outline Package SP48 Package Diagrams Lead 300-Mil Soic S24.3/SZ24.3 PIN 1 IDDSG Issue Orig. Description of Change DateDocument History TYJ

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.
Top Page Image Contents