Cypress CY7C63513C Interrupts, Global Interrupt Enable Register Addr, Gpio DAC, EPA2 EPA1 EPA0

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CY7C63413C

CY7C63513C

CY7C63613C

The “Single Step” (bit 1) is provided to support a hardware debugger. When single step is set, the processor will execute one instruction and halt (clear the run bit). This bit must be cleared for normal operation.

The “Interrupt Mask” (bit 2) shows whether interrupts are enabled or disabled. The firmware has no direct control over this bit as writing a zero or one to this bit position will have no effect on interrupts. Instructions DI, EI, and RETI manipulate the internal hardware that controls the state of the interrupt mask bit in the Processor Status and Control Register.

Writing a “1” to “Suspend, Wait for Interrupts” (bit 3) will halt the processor and cause the microcontroller to enter the “suspend” mode that significantly reduces power consumption. A pending interrupt or bus activity will cause the device to come out of suspend. After coming out of suspend, the device will resume firmware execution at the instruction following the IOWR which put the part into suspend. An IOWR that attempts to put the part into suspend will be ignored if either bus activity or an interrupt is pending.

The “Power-on Reset” (bit 4) is only set to “1” during a power on reset. The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a Power On condition or a Watch Dog Timeout. PORS is used to determine suspend start-up timer value of 128 ∝s or 96 ms.

The “USB Bus Reset” (bit 5) will occur when a USB bus reset is received. The USB Bus Reset is a singled-ended zero (SE0) that lasts more than 8 microseconds. An SE0 is defined as the condition in which both the D+ line and the D– line are LOW at the same time. When the SIE detects this condition, the USB Bus Reset bit is set in the Processor Status and Control register and an USB Bus Reset interrupt is generated. Please note this is an interrupt to the microcontroller and does not actually reset the processor.

The “Watch Dog Reset” (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went for more than 8 ms between watch dog clears.

The “IRQ Pending” (bit 7) indicates one or more of the inter- rupts has been recognized as active. The interrupt acknowledge sequence should clear this bit until the next interrupt is detected.

During Power-on Reset, the Processor Status and Control Register is set to 00010001, which indicates a Power-on Reset (bit 4 set) has occurred and no interrupts are pending (bit 7 clear) yet.

During a Watch Dog Reset, the Processor Status and Control Register is set to 01000001, which indicates a Watch Dog Reset (bit 6 set) has occurred and no interrupts are pending (bit 7 clear) yet.

Interrupts

All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a “1” to a bit position enables the interrupt associated with that bit position. During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared, effectively disabling all interrupts.

Pending interrupt requests are recognized during the last clock cycle of the current instruction. When servicing an interrupt, the hardware will first disable all interrupts by clearing the Interrupt Enable bit in the Processor Status and Control Register. Next, the interrupt latch of the current interrupt is cleared. This is followed by a CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt Vector). The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruction. Inter- rupts can be nested to a level limited only by the available stack space.

The Program Counter value as well as the Carry and Zero flags (CF, ZF) are automatically stored onto the Program Stack by the CALL instruction as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the processor state is preserved and restored during an interrupt. The PUSH A instruction should be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used just before the RETI instruction to restore the accumulator value. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed.

Table 25.Global Interrupt Enable Register

 

Addr: 0x20

 

Global Interrupt Enable Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

Reserved

GPIO

 

DAC

Reserved

 

1.024-ms

128-∝sec

USB Bus RST

 

 

 

Interrupt

 

Interrupt

 

 

Interrupt

Interrupt

Interrupt

 

 

 

Enable

 

Enable

 

 

Enable

Enable

Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

R/W

 

 

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

Table 26.USB End Point Interrupt Enable Register

 

 

 

 

 

 

 

 

 

 

 

Addr: 0x21

USB End Point Interrupt Enable Register

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

Reserved

Reserved

 

Reserved

Reserved

 

EPA2

EPA1

EPA0

 

 

 

 

 

 

 

 

Interrupt

Interrupt

Interrupt

 

 

 

 

 

 

 

 

Enable

Enable

Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-08027 Rev. *B

 

 

 

 

 

 

 

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Contents Functional Overview FeaturesCypress Semiconductor Corporation CY7C63413C CY7C63513C CY7C63613C Logic Block Diagram Programming Model Pin DefinitionsButtons EQU 10h MOV A,buttons Bit Data Stack Pointer DSPAddress Modes MOV A,DSPINITOperand Opcode Cycles Instruction Set SummaryProgram Memory begins here Memory OrganizationProgram Memory Organization ReservedData Memory Organization USB Address A, Endpoint 0 counter register Register SummaryO Register Summary Register Name Address Read/Write FunctionClocking ResetAddr Port 2 Data General Purpose I/O PortsPin Addr Port 1 DataAddr Port 0 Interrupt Enable Port 0 Interrupt EnableGpio Interrupt Enable Ports Gpio Configuration PortCmos Output + defaultAddr Gpio Configuration Register DAC PortDAC Isink Registers DAC Port Interrupt EnableAddr DAC Port Interrupt Enable DAC Port InterruptsUSB Serial Interface Engine SIE USB Device Byte count USB Device Counter RegistersAddr 0x11, 0x13 USB Device Counter Registers Data 0/1Timer MSB Timer Register Addr Timer Register MSB Bit Free-running TimerTimer LSB Timer Register Addr Timer Register LSBGpio DAC Global Interrupt Enable Register AddrUSB End Point Interrupt Enable Register Addr InterruptsInterrupt Latency Interrupt VectorsInterrupt Vector Assignments Interrupt Vector Number ROM Address FunctionNAK USB Register Mode EncodingTruth Tables EncodingEncoding What the SIE does to Mode bits PID Status bits Interrupt?Control Read Set End Point ModeSetup Packet if accepting Control WriteOut endpoint USB Interface Power-On ResetAbsolute Maximum Ratings Parameter Min Max Unit Conditions GeneralSwitching Characteristics Differential Data Lines Range Ordering InformationOrdering Code Package Package Type Operating SizeDIe Pad Locations in microns Pad # Pin Name Die Pad LocationsLead Shrunk Small Outline Package SP48 Package DiagramsLead 600-Mil Molded DIP P2 PIN 1 ID Package Diagrams Lead 300-Mil Soic S24.3/SZ24.3TYJ Issue Orig. Description of Change DateDocument History DSG

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.
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