Cypress CY7C63613C, CY7C63513C O Register Summary, Register Name Address Read/Write Function

Page 9

CY7C63413C

CY7C63513C

CY7C63613C

I/O Register Summary

I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumu-

Table 1. I/O Register Summary

lator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.

Register Name

I/O Address

Read/Write

Function

Port 0 Data

0x00

R/W

GPIO Port 0

 

 

 

 

Port 1 Data

0x01

R/W

GPIO Port 1

 

 

 

 

Port 2 Data

0x02

R/W

GPIO Port 2

 

 

 

 

Port 3 Data

0x03

R/W

GPIO Port 3

 

 

 

 

Port 0 Interrupt Enable

0x04

W

Interrupt enable for pins in Port 0

 

 

 

 

Port 1 Interrupt Enable

0x05

W

Interrupt enable for pins in Port 1

 

 

 

 

Port 2 Interrupt Enable

0x06

W

Interrupt enable for pins in Port 2

 

 

 

 

Port 3 Interrupt Enable

0x07

W

Interrupt enable for pins in Port 3

 

 

 

 

GPIO Configuration

0x08

R/W

GPIO Ports Configurations

 

 

 

 

USB Device Address A

0x10

R/W

USB Device Address A

EP A0 Counter Register

0x11

R/W

USB Address A, Endpoint 0 counter register

 

 

 

 

EP A0 Mode Register

0x12

R/W

USB Address A, Endpoint 0 configuration register

 

 

 

 

EP A1 Counter Register

0x13

R/W

USB Address A, Endpoint 1 counter register

 

 

 

 

EP A1 Mode Register

0x14

R/C

USB Address A, Endpoint 1 configuration register

 

 

 

 

EP A2 Counter Register

0x15

R/W

USB Address A, Endpoint 2 counter register

 

 

 

 

EP A2 Mode Register

0x16

R/C

USB Address A, Endpoint 2 configuration register

 

 

 

 

USB Status & Control

0x1F

R/W

USB upstream port traffic status and control register

 

 

 

 

Global Interrupt Enable

0x20

R/W

Global interrupt enable register

Endpoint Interrupt Enable

0x21

R/W

USB endpoint interrupt enables

 

 

 

 

Timer (LSB)

0x24

R

Lower eight bits of free-running timer (1 MHz)

 

 

 

 

Timer (MSB)

0x25

R

Upper four bits of free-running timer that are latched

 

 

 

when the lower eight bits are read.

WDR Clear

0x26

W

Watch Dog Reset clear

 

 

 

 

DAC Data

0x30

R/W

DAC I/O[2]

DAC Interrupt Enable

0x31

W

Interrupt enable for each DAC pin

 

 

 

 

DAC Interrupt Polarity

0x32

W

Interrupt polarity for each DAC pin

 

 

 

 

DAC Isink

0x38-0x3F

W

One four bit sink current register for each DAC pin

 

 

 

 

Processor Status & Control

0xFF

R/W

Microprocessor status and control

Note:

2. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused GPIO pins.

Document #: 38-08027 Rev. *B

Page 9 of 32

[+] Feedback

Image 9
Contents Features Functional OverviewCypress Semiconductor Corporation CY7C63413C CY7C63513C CY7C63613C Logic Block Diagram Programming Model Pin DefinitionsAddress Modes Bit Data Stack Pointer DSPMOV A,DSPINIT Buttons EQU 10h MOV A,buttonsOperand Opcode Cycles Instruction Set SummaryProgram Memory Organization Memory OrganizationReserved Program Memory begins hereData Memory Organization O Register Summary Register SummaryRegister Name Address Read/Write Function USB Address A, Endpoint 0 counter registerClocking ResetPin General Purpose I/O PortsAddr Port 1 Data Addr Port 2 DataGpio Interrupt Enable Ports Port 0 Interrupt EnableGpio Configuration Port Addr Port 0 Interrupt EnableAddr Gpio Configuration Register + defaultDAC Port Cmos OutputAddr DAC Port Interrupt Enable DAC Port Interrupt EnableDAC Port Interrupts DAC Isink RegistersUSB Serial Interface Engine SIE USB Device Addr 0x11, 0x13 USB Device Counter Registers USB Device Counter RegistersData 0/1 Byte countTimer LSB Timer Register Bit Free-running TimerAddr Timer Register LSB Timer MSB Timer Register Addr Timer Register MSBUSB End Point Interrupt Enable Register Addr Global Interrupt Enable Register AddrInterrupts Gpio DACInterrupt Vector Assignments Interrupt VectorsInterrupt Vector Number ROM Address Function Interrupt LatencyTruth Tables USB Register Mode EncodingEncoding NAKEncoding What the SIE does to Mode bits PID Status bits Interrupt?Setup Packet if accepting Set End Point ModeControl Write Control ReadOut endpoint Absolute Maximum Ratings Power-On ResetParameter Min Max Unit Conditions General USB InterfaceSwitching Characteristics Differential Data Lines Ordering Code Ordering InformationPackage Package Type Operating Size RangeDIe Pad Locations in microns Pad # Pin Name Die Pad LocationsPackage Diagrams Lead Shrunk Small Outline Package SP48Lead 600-Mil Molded DIP P2 PIN 1 ID Package Diagrams Lead 300-Mil Soic S24.3/SZ24.3Document History Issue Orig. Description of Change DateDSG TYJ

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.