Cypress CY7C63613C Bit Free-running Timer, Timer LSB Timer Register, Addr Timer Register LSB, Irq

CY7C63413C

CY7C63513C

CY7C63613C

12-bit Free-running Timer

The 12-bit timer provides two interrupts (128 ∝s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the

Timer (LSB)

Table 22.Timer Register

upper 4 bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is actually reading the count stored in the temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time.

Addr: 0x24			Timer Register (LSB)
Timer	Timer	Timer	Timer	Timer	Timer	Timer	Timer
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
R	R	R	R	R	R	R	R
Timer (MSB)
Table 23.Timer Register
Addr: 0x25			Timer Register (MSB)
Reserved	Reserved	Reserved	Reserved	Timer	Timer	Timer	Timer
				Bit 11	Bit 10	Bit 9	Bit 8
				R	R	R	R

1.024-ms interrupt

128-∝s interrupt

11 10 9

8

7

6

5

4

3

2

1

0

1-MHz clock

L3		L2		L1		L0
	D3		D2		D1		D0	D7

D6 D5 D4 D3 D2 D1

D0

					8	To Timer Register
		Figure 6. Timer Block Diagram
Processor Status and Control Register
Table 24.Processor Status and Control Register
Addr: 0xFF		Processor Status and Control Register					POR Default: 0x0101
							WDC Reset: 0x41
7	6	5	4	3	2		1	0
IRQ	Watch Dog	USB Bus	Power-on	Suspend,Wait	Interrupt		Single Step	Run
Pending	Reset	Reset	Reset	for Interrupt	Mask
R	R/W	R/W	R/W	R/W	R		R/W	R/W

The “Run” (bit 0) is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the end of the current instruction. The processor remains

halted until a reset (Power On or Watch Dog). Notice, when writing to the processor status and control register, the run bit should always be written as a “1.”

Document #: 38-08027 Rev. *B Page 18 of 32

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